#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/suspend/rockchip-pm.h>
+#include <dt-bindings/suspend/rockchip-rk3368.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sensor-dev.h>
};
};
+ efuse_256@ffb00000 {
+ compatible = "rockchip,rk3368-efuse-256";
+ reg = <0x0 0xffb00000 0x0 0x8>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
rockchip,broadcast = <1>;
};
+ timer@ff810020 {
+ compatible = "rockchip,timer";
+ reg = <0x0 0xff810020 0x0 0x20>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,percpu = <0>;
+ };
+
sram: sram@ff8c0000 {
compatible = "mmio-sram";
reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
reg = <0x0 0xff400000 0x0 0x4000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
nandc_id = <0>;
- clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
+ clocks = <&clk_nandc0>, <&clk_gates20 9>, <&clk_gates20 11>;
clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
};
rockchip_clocks_enable: clocks-enable {
compatible = "rockchip,clocks-enable";
clocks =
- <&pd_vio>,
- <&pd_video>,
- <&pd_gpu_0>,
- <&pd_gpu_1>,
-
/*PLL*/
<&clk_apllb>,
<&clk_aplll>,
<&clk_gates12 9>,/*hclk_rom*/
/*PD_ALIVE*/
- <&clk_gates22 13>,/*pclk_timer1*/
<&clk_gates22 12>,/*pclk_timer0*/
<&clk_gates22 9>,/*pclk_alive_niu*/
<&clk_gates22 8>,/*pclk_grf*/
<&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
<&clk_gates19 1>,/*pclk_peri_axi_matrix*/
+ <&clk_gates24 0>, /* g_clk_timer0 */
+ <&clk_gates24 1>, /* g_clk_timer1 */
+
<&fclk_mcu>,
<&stclk_mcu>,
<&clk_gates7 0>;/*clk_jtag*/
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c0_xfer>;
pinctrl-1 = <&i2c0_gpio>;
+ pinctrl-2 = <&i2c0_sleep>;
gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates12 2>;
rockchip,check-idle = <1>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c1_xfer>;
pinctrl-1 = <&i2c1_gpio>;
+ pinctrl-2 = <&i2c1_sleep>;
gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates12 3>;
rockchip,check-idle = <1>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c2_xfer>;
pinctrl-1 = <&i2c2_gpio>;
+ pinctrl-2 = <&i2c2_sleep>;
gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates19 11>;
rockchip,check-idle = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c3_xfer>;
pinctrl-1 = <&i2c3_gpio>;
+ pinctrl-2 = <&i2c3_sleep>;
gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates19 12>;
rockchip,check-idle = <1>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c4_xfer>;
pinctrl-1 = <&i2c4_gpio>;
+ pinctrl-2 = <&i2c4_sleep>;
gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates19 13>;
rockchip,check-idle = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&i2c5_xfer>;
pinctrl-1 = <&i2c5_gpio>;
+ pinctrl-2 = <&i2c5_sleep>;
gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates19 14>;
rockchip,check-idle = <1>;
rockchip,cru = <&cru>;
rockchip,prop = <PRMRY>;
rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <0>;
+ rockchip,iommu-enabled = <1>;
reg = <0x0 0xff930000 0x0 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
/*pinctrl-names = "default", "gpio";
300000 1200000
400000 1200000
>;
+ bd-freq-table = <
+ /* bandwidth freq */
+ 2700 792000
+ 2600 600000
+ 2280 456000
+ 1560 396000
+ 1020 324000
+ 720 240000
+ >;
channel = <2>;
status = "disabled";
};
ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
compatible = "rockchip,ion-heap";
rockchip,ion_heap = <4>;
- reg = <0x00000000 0x08000000>; /* 512MB */
+ reg = <0x00000000 0x00000000>; /* 0MB */
};
rockchip,ion-heap@0 { /* VMALLOC HEAP */
compatible = "rockchip,ion-heap";
vpu: vpu_service {
compatible = "rockchip,vpu_sub";
- iommu_enabled = <0>;
+ iommu_enabled = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
hevc: hevc_service {
compatible = "rockchip,hevc_sub";
- iommu_enabled = <0>;
+ iommu_enabled = <1>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
dev_mode = <1>;
iep: iep@ff900000 {
compatible = "rockchip,iep";
- iommu_enabled = <0>;
+ iommu_enabled = <1>;
reg = <0x0 0xff900000 0x0 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates16 2>, <&clk_gates16 3>;
dbgname = "vpu";
compatible = "rockchip,vpu_mmu";
reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
- interrupt-names = "vpu_mmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /*need to fix*/
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
};
- rockchip_suspend {
+ rockchip_suspend: rockchip_suspend {
rockchip,ctrbits = <
(0
- |RKPM_CTR_PWR_DMNS
- |RKPM_CTR_GTCLKS
- |RKPM_CTR_PLLS
- |RKPM_CTR_GPIOS
- /*
- |RKPM_CTR_SYSCLK_DIV
- |RKPM_CTR_IDLEAUTO_MD
- |RKPM_CTR_ARMOFF_LPMD
- */
- |RKPM_CTR_ARMOFF_LOGDP_LPMD
+ | RKPM_SLP_ARMOFF
+ | RKPM_SLP_PMU_PLLS_PWRDN
+ /*| RKPM_SLP_PMU_PMUALIVE_32K
+ | RKPM_SLP_SFT_PLLS_DEEP
+ | RKPM_SLP_PMU_DIS_OSC */
+ | RKPM_SLP_SFT_PD_NBSCUS
)
>;
- rockchip,pmic-suspend_gpios = <
- /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
- >;
- rockchip,pmic-resume_gpios = <
- /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
- >;
};
isp: isp@ff910000{
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
- rockchip,isp,iommu_enable = <0>;
+ rockchip,isp,iommu_enable = <1>;
status = "okay";
};
};
};
+ usbphy: phy {
+ compatible = "rockchip,rk3368-usb-phy";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x700>;
+ };
+
+ usbphy1: usb-phy1 {
+ #phy-cells = <0>;
+ reg = <0x728>;
+ };
+ };
+
usb0: usb@ff580000 {
compatible = "rockchip,rk3368_usb20_otg";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 1>, <&clk_gates20 3>;
clock-names = "clk_usbphy0", "hclk_ehci";
+ phys = <&usbphy1>;
+ phy-names = "usb";
//resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
// <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
//reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
output-low;
};
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
<0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ i2c0_sleep: i2c0-sleep {
+ rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
+ <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
i2c1 {
rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
<2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ i2c1_sleep: i2c1-sleep {
+ rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 GPIO_C6 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
i2c2 {
i2c2_gpio: i2c2-gpio {
rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
<0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
+ };
+ i2c2_sleep: i2c2-sleep {
+ rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_input_high>,
+ <0 GPIO_B1 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
i2c3 {
rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
<1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ i2c3_sleep: i2c3-sleep {
+ rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 GPIO_C1 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
i2c4 {
rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ i2c4_sleep: i2c4-sleep {
+ rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 GPIO_D1 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
i2c5 {
rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
<3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ i2c5_sleep: i2c5-sleep {
+ rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 GPIO_D3 RK_FUNC_GPIO &pcfg_input_high>;
+ };
};
uart0 {
projects / firefly-linux-kernel-4.4.55.git / blobdiff