temp revert rk change

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-tegra / include / mach / spdif.h

diff --git a/arch/arm/mach-tegra/include/mach/spdif.h b/arch/arm/mach-tegra/include/mach/spdif.h
index cbfaba73c6ca9fb36e2f7fbcb4030c131d60d010..96103fae91b1930c176f1e2648e102e35219023c 100644 (file)
--- a/arch/arm/mach-tegra/include/mach/spdif.h
+++ b/arch/arm/mach-tegra/include/mach/spdif.h
@@ -293,8 +293,8 @@
 
 /* Number of RX USR.FIFO levels with valid data. */
 #define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT         (24)
-#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK          (0x1f << \
-               SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK                  \
+               (0x1f << SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT)
 
 /* Clear Transmitter User FIFO (TX USR.FIFO) */
 #define SPDIF_DATA_FIFO_CSR_0_TU_CLR                    (1<<23)
@@ -310,8 +310,8 @@
 #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4           (3)
 
 #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT         (21)
-#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK          (0x3 << \
-               SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK                  \
+               (0x3 << SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
 #define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1_WORD_EMPTY                \
                (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 <<        \
                        SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
@@ -331,17 +331,17 @@
                ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT)
 
 /* Clear Receiver Data FIFO (RX DATA.FIFO). */
-#define SPDIF_DATA_FIFO_CSR_0_RX_CLR                           (1<<15)
+#define SPDIF_DATA_FIFO_CSR_0_RX_CLR                   (1<<15)
 
 /*
  * Rx FIFO Attention Level:
  * 11=12-slots-full, 10=8-slots-full, 01=4-slots-full, 00=1-slot-full.
  */
-#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT                 (13)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT         (13)
 #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_MASK                  \
                (0x3 << SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
 #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX1_WORD_FULL         \
-               (SPDIF_FIFO_ATN_LVL_ONE_SLOT <<                 \
+       (SPDIF_FIFO_ATN_LVL_ONE_SLOT <<                         \
                SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
 #define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX4_WORD_FULL         \
                (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS <<               \
@@ -355,8 +355,8 @@
 
 
 /* Number of RX DATA.FIFO levels with valid data */
-#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT            (8)
-#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD            \
+#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT    (8)
+#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD    \
        ((0x1f) << SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT)
 
 /* Clear Transmitter Data FIFO (TX DATA.FIFO) */
@@ -366,7 +366,7 @@
  * Tx FIFO Attention Level:
  * 11=12-slots-empty, 10=8-slots-empty, 01=4-slots-empty, 00=1-slot-empty
  */
-#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT                 (5)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT         (5)
 #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_MASK                  \
                (0x3 << SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
 #define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX1_WORD_FULL         \