#include <linux/resource.h>
#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/fsl_devices.h>
+#include <linux/serial_8250.h>
+#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
+#include <mach/dma.h>
static struct resource i2c_resource1[] = {
[0] = {
},
};
-
/* board files should fill in platform_data register the devices themselvs.
* See board-harmony.c for an example
*/
.resource = sdhci_resource4,
.num_resources = ARRAY_SIZE(sdhci_resource4),
};
+
+static struct resource w1_resources[] = {
+ [0] = {
+ .start = INT_OWR,
+ .end = INT_OWR,
+ .flags = IORESOURCE_IRQ
+ },
+ [1] = {
+ .start = TEGRA_OWR_BASE,
+ .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+struct platform_device tegra_w1_device = {
+ .name = "tegra_w1",
+ .id = -1,
+ .resource = w1_resources,
+ .num_resources = ARRAY_SIZE(w1_resources),
+};
+
+static struct resource tegra_udc_resources[] = {
+ [0] = {
+ .start = TEGRA_USB_BASE,
+ .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_USB,
+ .end = INT_USB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource tegra_usb1_resources[] = {
+ [0] = {
+ .start = TEGRA_USB_BASE,
+ .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_USB,
+ .end = INT_USB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource tegra_usb2_resources[] = {
+ [0] = {
+ .start = TEGRA_USB2_BASE,
+ .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_USB2,
+ .end = INT_USB2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource tegra_usb3_resources[] = {
+ [0] = {
+ .start = TEGRA_USB3_BASE,
+ .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_USB3,
+ .end = INT_USB3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
+
+static struct fsl_usb2_platform_data tegra_udc_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+struct platform_device tegra_udc_device = {
+ .name = "fsl-tegra-udc",
+ .id = -1,
+ .dev = {
+ .dma_mask = &tegra_udc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &tegra_udc_pdata,
+ },
+ .resource = tegra_udc_resources,
+ .num_resources = ARRAY_SIZE(tegra_udc_resources),
+};
+
+static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device tegra_ehci1_device = {
+ .name = "tegra-ehci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &tegra_ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = tegra_usb1_resources,
+ .num_resources = ARRAY_SIZE(tegra_usb1_resources),
+};
+
+struct platform_device tegra_ehci2_device = {
+ .name = "tegra-ehci",
+ .id = 1,
+ .dev = {
+ .dma_mask = &tegra_ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = tegra_usb2_resources,
+ .num_resources = ARRAY_SIZE(tegra_usb2_resources),
+};
+
+struct platform_device tegra_ehci3_device = {
+ .name = "tegra-ehci",
+ .id = 2,
+ .dev = {
+ .dma_mask = &tegra_ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = tegra_usb3_resources,
+ .num_resources = ARRAY_SIZE(tegra_usb3_resources),
+};
+
+static struct resource tegra_otg_resources[] = {
+ [0] = {
+ .start = TEGRA_USB_BASE,
+ .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_USB,
+ .end = INT_USB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device tegra_otg_device = {
+ .name = "tegra-otg",
+ .id = -1,
+ .resource = tegra_otg_resources,
+ .num_resources = ARRAY_SIZE(tegra_otg_resources),
+};
+
+static struct resource i2s_resource1[] = {
+ [0] = {
+ .start = INT_I2S1,
+ .end = INT_I2S1,
+ .flags = IORESOURCE_IRQ
+ },
+ [1] = {
+ .start = TEGRA_DMA_REQ_SEL_I2S_1,
+ .end = TEGRA_DMA_REQ_SEL_I2S_1,
+ .flags = IORESOURCE_DMA
+ },
+ [2] = {
+ .start = TEGRA_I2S1_BASE,
+ .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct resource i2s_resource2[] = {
+ [0] = {
+ .start = INT_I2S2,
+ .end = INT_I2S2,
+ .flags = IORESOURCE_IRQ
+ },
+ [1] = {
+ .start = TEGRA_DMA_REQ_SEL_I2S2_1,
+ .end = TEGRA_DMA_REQ_SEL_I2S2_1,
+ .flags = IORESOURCE_DMA
+ },
+ [2] = {
+ .start = TEGRA_I2S2_BASE,
+ .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct resource spdif_resource[] = {
+ [0] = {
+ .start = INT_SPDIF,
+ .end = INT_SPDIF,
+ .flags = IORESOURCE_IRQ
+ },
+ [1] = {
+ .start = TEGRA_DMA_REQ_SEL_SPD_I,
+ .end = TEGRA_DMA_REQ_SEL_SPD_I,
+ .flags = IORESOURCE_DMA
+ },
+ [2] = {
+ .start = TEGRA_SPDIF_BASE,
+ .end = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+struct platform_device tegra_i2s_device1 = {
+ .name = "i2s",
+ .id = 0,
+ .resource = i2s_resource1,
+ .num_resources = ARRAY_SIZE(i2s_resource1),
+};
+
+struct platform_device tegra_i2s_device2 = {
+ .name = "i2s",
+ .id = 1,
+ .resource = i2s_resource2,
+ .num_resources = ARRAY_SIZE(i2s_resource2),
+};
+
+struct platform_device tegra_spdif_device = {
+ .name = "spdif_out",
+ .id = -1,
+ .resource = spdif_resource,
+ .num_resources = ARRAY_SIZE(spdif_resource),
+};
+
+static struct resource tegra_gart_resources[] = {
+ [0] = {
+ .name = "mc",
+ .flags = IORESOURCE_MEM,
+ .start = TEGRA_MC_BASE,
+ .end = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
+ },
+ [1] = {
+ .name = "gart",
+ .flags = IORESOURCE_MEM,
+ .start = TEGRA_GART_BASE,
+ .end = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
+ }
+};
+
+struct platform_device tegra_gart_device = {
+ .name = "tegra_gart",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(tegra_gart_resources),
+ .resource = tegra_gart_resources
+};
+
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = INT_CPU0_PMU_INTR,
+ .end = INT_CPU0_PMU_INTR,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = INT_CPU1_PMU_INTR,
+ .end = INT_CPU1_PMU_INTR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
+#define CLK_RESET_RST_SOURCE 0x0
+static struct resource tegra_wdt_resources[] = {
+ [0] = {
+ .start = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
+ .end = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = TEGRA_TMR1_BASE,
+ .end = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = INT_TMR1,
+ .end = INT_TMR1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device tegra_wdt_device = {
+ .name = "tegra_wdt",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(tegra_wdt_resources),
+ .resource = tegra_wdt_resources,
+};
+
+static struct resource tegra_pwfm0_resource = {
+ .start = TEGRA_PWFM0_BASE,
+ .end = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource tegra_pwfm1_resource = {
+ .start = TEGRA_PWFM1_BASE,
+ .end = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource tegra_pwfm2_resource = {
+ .start = TEGRA_PWFM2_BASE,
+ .end = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource tegra_pwfm3_resource = {
+ .start = TEGRA_PWFM3_BASE,
+ .end = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+struct platform_device tegra_pwfm0_device = {
+ .name = "tegra_pwm",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &tegra_pwfm0_resource,
+};
+
+struct platform_device tegra_pwfm1_device = {
+ .name = "tegra_pwm",
+ .id = 1,
+ .num_resources = 1,
+ .resource = &tegra_pwfm1_resource,
+};
+
+struct platform_device tegra_pwfm2_device = {
+ .name = "tegra_pwm",
+ .id = 2,
+ .num_resources = 1,
+ .resource = &tegra_pwfm2_resource,
+};
+
+struct platform_device tegra_pwfm3_device = {
+ .name = "tegra_pwm",
+ .id = 3,
+ .num_resources = 1,
+ .resource = &tegra_pwfm3_resource,
+};
+
+static struct plat_serial8250_port tegra_uart0_port[] = {
+ [0] = {
+ .mapbase = TEGRA_UARTA_BASE,
+ .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
+ .irq = INT_UARTA,
+ },
+ [1] = {
+ .flags = 0,
+ },
+};
+
+static struct plat_serial8250_port tegra_uart1_port[] = {
+ [0] = {
+ .mapbase = TEGRA_UARTB_BASE,
+ .membase = IO_ADDRESS(TEGRA_UARTB_BASE),
+ .irq = INT_UARTB,
+ },
+ [1] = {
+ .flags = 0,
+ },
+};
+
+static struct plat_serial8250_port tegra_uart2_port[] = {
+ [0] = {
+ .mapbase = TEGRA_UARTC_BASE,
+ .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
+ .irq = INT_UARTC,
+ },
+ [1] = {
+ .flags = 0,
+ },
+};
+
+static struct plat_serial8250_port tegra_uart3_port[] = {
+ [0] = {
+ .mapbase = TEGRA_UARTD_BASE,
+ .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
+ .irq = INT_UARTD,
+ },
+ [1] = {
+ .flags = 0,
+ },
+};
+
+static struct plat_serial8250_port tegra_uart4_port[] = {
+ [0] = {
+ .mapbase = TEGRA_UARTE_BASE,
+ .membase = IO_ADDRESS(TEGRA_UARTE_BASE),
+ .irq = INT_UARTE,
+ },
+ [1] = {
+ .flags = 0,
+ },
+};
+
+struct platform_device tegra_uart0_device = {
+ .name = "tegra_uart",
+ .id = 0,
+ .dev = {
+ .platform_data = tegra_uart0_port,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device tegra_uart1_device = {
+ .name = "tegra_uart",
+ .id = 1,
+ .dev = {
+ .platform_data = tegra_uart1_port,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device tegra_uart2_device = {
+ .name = "tegra_uart",
+ .id = 2,
+ .dev = {
+ .platform_data = tegra_uart2_port,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device tegra_uart3_device = {
+ .name = "tegra_uart",
+ .id = 3,
+ .dev = {
+ .platform_data = tegra_uart3_port,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device tegra_uart4_device = {
+ .name = "tegra_uart",
+ .id = 4,
+ .dev = {
+ .platform_data = tegra_uart4_port,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource tegra_grhost_resources[] = {
+ {
+ .start = TEGRA_HOST1X_BASE,
+ .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = TEGRA_DISPLAY_BASE,
+ .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = TEGRA_DISPLAY2_BASE,
+ .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = TEGRA_VI_BASE,
+ .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = TEGRA_ISP_BASE,
+ .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = TEGRA_MPE_BASE,
+ .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_SYNCPT_THRESH_BASE,
+ .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = INT_HOST1X_MPCORE_GENERAL,
+ .end = INT_HOST1X_MPCORE_GENERAL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device tegra_grhost_device = {
+ .name = "tegra_grhost",
+ .id = -1,
+ .resource = tegra_grhost_resources,
+ .num_resources = ARRAY_SIZE(tegra_grhost_resources),
+};
+
+static struct resource tegra_avp_resources[] = {
+ [0] = {
+ .start = INT_SHR_SEM_INBOX_IBF,
+ .end = INT_SHR_SEM_INBOX_IBF,
+ .flags = IORESOURCE_IRQ,
+ .name = "mbox_from_avp_pending",
+ },
+};
+
+struct platform_device tegra_avp_device = {
+ .name = "tegra-avp",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(tegra_avp_resources),
+ .resource = tegra_avp_resources,
+ .dev = {
+ .coherent_dma_mask = 0xffffffffULL,
+ },
+};
projects / firefly-linux-kernel-4.4.55.git / blobdiff