ARM: tegra: clock: Fix cpu pll table entry for 608MHz

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-tegra / Kconfig

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a57713c1954abe0ca329648d7fc398c8ac3d64f7..6f28e0e73469d72fc78f93191de02a269aa2485a 100644 (file)
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
        select CPU_V7
        select ARM_GIC
        select ARCH_REQUIRE_GPIOLIB
+       select ARM_ERRATA_742230
        help
          Support for NVIDIA Tegra AP20 and T20 processors, based on the
          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -21,7 +22,12 @@ comment "Tegra board type"
 config MACH_HARMONY
        bool "Harmony board"
        help
-         Support for nVidia Harmony development platform
+         Support for NVIDIA Harmony development platform
+
+config MACH_VENTANA
+       bool "Ventana board"
+       help
+         Support for NVIDIA Ventana development platform
 
 choice
         prompt "Low-level debug console UART"
@@ -47,4 +53,39 @@ config TEGRA_DEBUG_UARTE
 
 endchoice
 
+config TEGRA_SYSTEM_DMA
+       bool "Enable system DMA driver for NVIDIA Tegra SoCs"
+       default y
+       help
+         Adds system DMA functionality for NVIDIA Tegra SoCs, used by
+         several Tegra device drivers
+
+config TEGRA_PWM
+       tristate "Enable PWM driver"
+       select HAVE_PWM
+       help
+         Enable support for the Tegra PWM controller(s).
+
 endif
+
+config TEGRA_CPU_DVFS
+       bool "Enable voltage scaling on Tegra CPU"
+       default y
+
+config TEGRA_CORE_DVFS
+       bool "Enable voltage scaling on Tegra core"
+       depends on TEGRA_CPU_DVFS
+       default y
+
+config TEGRA_IOVMM_GART
+       bool "Enable I/O virtual memory manager for GART"
+       depends on ARCH_TEGRA_2x_SOC
+       default y
+       select TEGRA_IOVMM
+       help
+         Enables support for remapping discontiguous physical memory
+         shared with the operating system into contiguous I/O virtual
+         space through the GART hardware included on Tegra SoCs
+
+config TEGRA_IOVMM
+       bool