ARM: SAMSUNG: register uart clocks to clock lookup list

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-s3c64xx / clock.c

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d7a3dc5a9eff3272aa84609c88f3f84465..2addd988141cd08ac86fbc03521e4ebbf3430ffe 100644 (file)
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -616,16 +616,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
                .sources        = &clkset_uhost,
        }, {
-               .clk    = {
-                       .name           = "uclk1",
-                       .ctrlbit        = S3C_CLKCON_SCLK_UART,
-                       .enable         = s3c64xx_sclk_ctrl,
-               },
-               .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
-               .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
-               .sources        = &clkset_uart,
-       }, {
-/* Where does UCLK0 come from? */
                .clk    = {
                        .name           = "spi-bus",
                        .devname        = "s3c64xx-spi.0",
@@ -695,6 +685,18 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
 
+/* Where does UCLK0 come from? */
+static struct clksrc_clk clk_sclk_uclk = {
+       .clk    = {
+               .name           = "uclk1",
+               .ctrlbit        = S3C_CLKCON_SCLK_UART,
+               .enable         = s3c64xx_sclk_ctrl,
+       },
+       .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
+       .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
+       .sources        = &clkset_uart,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -703,6 +705,15 @@ static struct clksrc_clk *init_parents[] = {
        &clk_mout_mpll,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+       &clk_sclk_uclk,
+};
+
+static struct clk_lookup s3c64xx_clk_lookup[] = {
+       CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+       CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+};
+
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -811,6 +822,8 @@ static struct clk *clks[] __initdata = {
 void __init s3c64xx_register_clocks(unsigned long xtal, 
                                    unsigned armclk_divlimit)
 {
+       unsigned int cnt;
+
        armclk_mask = armclk_divlimit;
 
        s3c24xx_register_baseclocks(xtal);
@@ -823,5 +836,9 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
 
        s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+       for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
+               s3c_register_clksrc(clksrc_cdev[cnt], 1);
+       clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
+
        s3c_pwmclk_init();
 }