arm64: configs: synchronize with other 3399 config for 3399 linux

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-rockchip / pm-rk3188.c

diff --git a/arch/arm/mach-rockchip/pm-rk3188.c b/arch/arm/mach-rockchip/pm-rk3188.c
old mode 100644 (file)
new mode 100755 (executable)
index e35f296..c59b509
--- a/arch/arm/mach-rockchip/pm-rk3188.c
+++ b/arch/arm/mach-rockchip/pm-rk3188.c
@@ -167,6 +167,7 @@ static void  inline uart_printch(char byte)
         
         rkpm_udelay(1);
         
+write_uart:
        writel_relaxed(byte, RK_DEBUG_UART_VIRT);
        dsb();
 
@@ -174,11 +175,13 @@ static void  inline uart_printch(char byte)
        while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
                barrier();
     
+       if (byte == '\n') {
+               byte = '\r';
+               goto write_uart;
+       }
+
          cru_writel(reg_save[0]|0x1<<((u_pclk_id%16)+16),RK3188_CRU_GATEID_CONS(u_clk_id));         
          cru_writel(reg_save[1]|0x1<<((u_pclk_id%16)+16),RK3188_CRU_GATEID_CONS(u_pclk_id));
-        
-       if (byte == '\n')
-               uart_printch('\r');
 }
 
 void PIE_FUNC(sram_printch)(char byte)
@@ -279,6 +282,7 @@ static void gtclks_resume(void)
 
 #define power_off_pll(id) \
        cru_writel(RK3188_PLL_PWR_DN_W_MSK | RK3188_PLL_PWR_DN, RK3188_PLL_CONS((id), 3))
+#if 0
 
 static void pm_pll_wait_lock(u32 pll_idx)
 {
@@ -310,12 +314,12 @@ static void power_on_pll(u32 pll_id)
         cru_writel(RK3188_PLL_PWR_DN_W_MSK | RK3188_PLL_PWR_ON, RK3188_PLL_CONS((pll_id), 3));
         pm_pll_wait_lock((pll_id));
 }
-
+#endif
 static u32 clk_sel0, clk_sel1, clk_sel10;
 static u32 cpll_con3;
 static u32 cru_mode_con;
 
-void plls_suspend(void)
+static void plls_suspend(void)
 {
     cru_mode_con = cru_readl(RK3188_CRU_MODE_CON);
     cru_writel(RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID), RK3188_CRU_MODE_CON);
@@ -357,7 +361,7 @@ void plls_suspend(void)
 
 }
 
-void plls_resume(void)
+static void plls_resume(void)
 {
     //gpll
        
@@ -451,7 +455,7 @@ void PIE_FUNC(sysclk_resume)(u32 sel_clk)
 
 }
 
-void clks_gating_suspend_init(void)
+static void clks_gating_suspend_init(void)
 {
     // get clk gating info
     p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
@@ -530,7 +534,7 @@ static  void rkpm_prepare(void)
        rk30_pm_dump_inten();
         #ifdef CONFIG_DDR_TEST
         // memory tester
-        ddr_testmode();
+        //ddr_testmode();
         #endif
 }
 
@@ -562,7 +566,6 @@ static u32 gpios_data[2];
 
 static void __init  rk3188_suspend_init(void)
 {
-
     struct device_node *parent;
     u32 pm_ctrbits;