#include <linux/mfd/rk808.h>
#include <linux/mfd/ricoh619.h>
#include <linux/regulator/rk29-pwm-regulator.h>
+#ifdef CONFIG_MFD_RT5025
+#include <linux/mfd/rt5025.h>
+#endif
+#include <plat/efuse.h>
#ifdef CONFIG_CW2015_BATTERY
#include <linux/power/cw2015_battery.h>
#if defined(CONFIG_LCDC0_RK3066B) || defined(CONFIG_LCDC0_RK3188)
struct rk29fb_info lcdc0_screen_info = {
+#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC0) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
+ .prop = EXTEND, //extend display device
+ .io_init = NULL,
+ .io_disable = NULL,
+ .io_enable = NULL,
+ .set_screen_info = hdmi_init_lcdc,
+#else
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
+#endif
};
#endif
#if defined(CONFIG_LCDC1_RK3066B) || defined(CONFIG_LCDC1_RK3188)
struct rk29fb_info lcdc1_screen_info = {
- #if defined(CONFIG_RK_HDMI)
- .prop = EXTEND, //extend display device
- .lcd_info = NULL,
+#if defined(CONFIG_RK_HDMI) && defined(CONFIG_HDMI_SOURCE_LCDC1) && defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
+ .prop = EXTEND, //extend display device
+ .io_init = NULL,
+ .io_disable = NULL,
+ .io_enable = NULL,
.set_screen_info = hdmi_init_lcdc,
- #endif
+#else
+ .prop = PRMRY, //primary display device
+ .io_init = rk_fb_io_init,
+ .io_disable = rk_fb_io_disable,
+ .io_enable = rk_fb_io_enable,
+ .set_screen_info = set_lcd_info,
+#endif
};
#endif
else
{
gpio_direction_output(RK616_RST_PIN, GPIO_HIGH);
- msleep(100);
+ msleep(2);
gpio_direction_output(RK616_RST_PIN, GPIO_LOW);
- msleep(100);
+ msleep(10);
gpio_set_value(RK616_RST_PIN, GPIO_HIGH);
}
}
}
+static int rk616_power_deinit(void)
+{
+ gpio_set_value(RK616_PWREN_PIN,GPIO_LOW);
+ gpio_set_value(RK616_RST_PIN,GPIO_LOW);
+ gpio_free(RK616_PWREN_PIN);
+ gpio_free(RK616_RST_PIN);
+
+ return 0;
+}
+
static struct rk616_platform_data rk616_pdata = {
.power_init = rk616_power_on_init,
+ .power_deinit = rk616_power_deinit,
.scl_rate = RK616_SCL_RATE,
+ .lcd0_func = INPUT, //port lcd0 as input
+ .lcd1_func = INPUT, //port lcd1 as input
+ .lvds_ch_nr = 1, //the number of used lvds channel
+ .hdmi_irq = RK30_PIN2_PD6,
+ .spk_ctl_gpio = RK30_PIN2_PD7,
+ .hp_ctl_gpio = RK30_PIN2_PD7,
};
#endif
+
#ifdef CONFIG_SND_SOC_RK610
static int rk610_codec_io_init(void)
{
static struct cw_bat_platform_data cw_bat_platdata = {
.dc_det_pin = RK30_PIN0_PB2,
- .bat_low_pin = RK30_PIN0_PB1,
- .chg_ok_pin = RK30_PIN0_PA6,
.dc_det_level = GPIO_LOW,
+
+ .bat_low_pin = RK30_PIN0_PB1,
.bat_low_level = GPIO_LOW,
+ .chg_ok_pin = INVALID_GPIO,
.chg_ok_level = GPIO_HIGH,
+ .is_usb_charge = 0,
+ .chg_mode_sel_pin = INVALID_GPIO,
+ .chg_mode_sel_level = GPIO_HIGH,
+
.cw_bat_config_info = config_info,
};
.iomux = {
.name = NULL,
},
- }
+ },
+
+ .rts_gpio = { // UART_RTS
+ .io = RK30_PIN1_PA3,
+ .enable = GPIO_LOW,
+ .iomux = {
+ .name = "bt_rts",
+ .fgpio = GPIO1_A3,
+ .fmux = UART0_RTSN,
+ },
+ },
};
static struct platform_device device_mt6622 = {
static struct pmu_info tps65910_dcdc_info[] = {
{
.name = "vdd_core", //logic
- .min_uv = 1100000,
- .max_uv = 1100000,
+ .min_uv = 1200000,
+ .max_uv = 1200000,
},
{
.name = "vdd2", //ddr
#include "board-pmu-ricoh619.c"
#endif
+#ifdef CONFIG_MFD_RT5025
+#define RT5025_HOST_IRQ RK30_PIN0_PB3
+
+static struct pmu_info rt5025_dcdc_info[] = {
+ {
+ .name = "vdd_cpu", //arm
+ .min_uv = 1000000,
+ .max_uv = 1000000,
+ },
+ {
+ .name = "vdd_core", //logic
+ .min_uv = 1000000,
+ .max_uv = 1000000,
+ },
+
+ {
+ .name = "rt5025-dcdc3", //vccio
+ .min_uv = 3300000,
+ .max_uv = 3300000,
+ },
+
+};
+static struct pmu_info rt5025_ldo_info[] = {
+ {
+ .name = "rt5025-ldo1", //vcc18
+ .min_uv = 1800000,
+ .max_uv = 1800000,
+ },
+ {
+ .name = "rt5025-ldo2", //vddjetta
+ .min_uv = 1200000,
+ .max_uv = 1200000,
+ },
+ {
+ .name = "rt5025-ldo3", //vdd10
+ .min_uv = 1200000,
+ .max_uv = 1200000,
+ },
+ {
+ .name = "rt5025-ldo4", //vccjetta
+ .min_uv = 3300000,
+ .max_uv = 3300000,
+ },
+ {
+ .name = "rt5025-ldo5", //vccio_wl
+ .min_uv = 1800000,
+ .max_uv = 1800000,
+ },
+ {
+ .name = "rt5025-ldo6", //vcc_tp
+ .min_uv = 3300000,
+ .max_uv = 3300000,
+ },
+
+ };
+
+#include "board-pmu-rt5025.c"
+#endif
+
static struct i2c_board_info __initdata i2c1_info[] = {
},
#endif
+#if defined (CONFIG_MFD_RT5025)
+ {
+ .type = "RT5025",
+ .addr = 0x35,
+ .flags = 0,
+ .irq = RT5025_HOST_IRQ,
+ .platform_data=&rt5025_data,
+ },
+#endif
+
#if defined (CONFIG_RTC_HYM8563)
{
.type = "rtc_hym8563",
#ifdef CONFIG_I2C4_RK30
static struct i2c_board_info __initdata i2c4_info[] = {
#if defined (CONFIG_MFD_RK616)
- {
- .type = "rk616",
- .addr = 0x50,
- .flags = 0,
- .platform_data = &rk616_pdata,
- },
+ {
+ .type = "rk616",
+ .addr = 0x50,
+ .flags = 0,
+ .platform_data = &rk616_pdata,
+ },
#endif
};
}
#endif
+ #if defined(CONFIG_MFD_RT5025)
+ if(pmic_is_rt5025()){
+ rt5025_power_off(); //rt5025 shutdown
+ }
+ #endif
+
gpio_direction_output(POWER_ON_PIN, GPIO_LOW);
while (1);
}
{.frequency = CPUFREQ_TABLE_END},
};
+static struct cpufreq_frequency_table dvfs_ddr_table_t[] = {
+ {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 950 * 1000},
+ {.frequency = 460 * 1000 + DDR_FREQ_NORMAL, .index = 1150 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
//if you board is good for volt quality,select dvfs_arm_table_volt_level0
#define dvfs_arm_table dvfs_arm_table_volt_level1
#define dvfs_gpu_table dvfs_gpu_table_volt_level1
//#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
//static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
//static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
+int get_max_freq(struct cpufreq_frequency_table *table)
+{
+ int i,temp=0;
+
+ for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
+ {
+ if(temp<table[i].frequency)
+ temp=table[i].frequency;
+ }
+ printk("get_max_freq=%d\n",temp);
+ return temp;
+}
void __init board_clock_init(void)
{
- rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
+ u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
+#if !defined(CONFIG_ARCH_RK3188)
+ if(get_max_freq(dvfs_gpu_table)<=(400*1000))
+ {
+ flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
+ }
+ else
+ flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
+#endif
+ rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
//dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
+#if defined(CONFIG_ARCH_RK3188)
+ if (rk_pll_flag() == 0)
+ dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
+ else
+ dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table_t);
+#else
dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
+#endif
}
MACHINE_START(RK30, "RK30board")
projects / firefly-linux-kernel-4.4.55.git / blobdiff