#else
#define SDRAM_SIZE SZ_512M
#endif
-#define PMEM_GPU_SIZE SZ_64M
+#define PMEM_GPU_SIZE SZ_16M
#define PMEM_UI_SIZE SZ_32M
#define PMEM_VPU_SIZE SZ_64M
#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY
#endif
#define MEM_FB_SIZE (3*SZ_2M)
#ifdef CONFIG_FB_WORK_IPP
+#ifdef CONFIG_FB_SCALING_OSD_1080P
+#define MEM_FBIPP_SIZE SZ_16M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
+#else
#define MEM_FBIPP_SIZE SZ_8M //1920 x 1080 x 2 x 2 //RGB565 = x2;RGB888 = x4
+#endif
#else
#define MEM_FBIPP_SIZE 0
#endif
.name = "pmem",
.start = PMEM_UI_BASE,
.size = PMEM_UI_SIZE,
- .no_allocator = 0,
+ .no_allocator = 1,
.cached = 1,
};
.off_mask = 1, /** Mask OFF while charging */
.trickle_ilim = 200, /** Trickle charge current limit, in mA */
.vsel = 4200, /** Target voltage, in mV */
- .eoc_iterm = 90, /** End of trickle charge current, in mA */
+ .eoc_iterm = 50, /** End of trickle charge current, in mA */
.fast_ilim = 500, /** Fast charge current limit, in mA */
- .timeout = 240, /** Charge cycle timeout, in minutes */
+ .timeout = 480, /** Charge cycle timeout, in minutes */
.syslo = 3300, /* syslo threshold, in mV*/
.sysok = 3500, /* sysko threshold, in mV*/
};
};
#endif
+#if defined(CONFIG_RK29_GPIO_SUSPEND)
+static void gpio_set_request(void)
+{
+ gpio_request(RK29_PIN6_PA0, NULL);
+ gpio_request(RK29_PIN6_PA1, NULL);
+ gpio_request(RK29_PIN6_PA2, NULL);
+ gpio_request(RK29_PIN6_PA3, NULL);
+ gpio_request(RK29_PIN6_PA4, NULL);
+ gpio_request(RK29_PIN6_PA5, NULL);
+ gpio_request(RK29_PIN6_PA6, NULL);
+
+ gpio_request(RK29_PIN2_PA5, NULL);
+ gpio_request(RK29_PIN2_PA4, NULL);
+ gpio_request(RK29_PIN2_PB0, NULL);
+ gpio_request(RK29_PIN2_PB1, NULL);
+ gpio_request(RK29_PIN2_PB2, NULL);
+ gpio_request(RK29_PIN2_PB3, NULL);
+
+ gpio_request(RK29_PIN1_PA4, NULL);
+ gpio_request(RK29_PIN1_PA3, NULL);
+
+ gpio_request(RK29_PIN2_PC7, NULL);
+ gpio_request(RK29_PIN2_PC6, NULL);
+ gpio_request(RK29_PIN2_PC5, NULL);
+ gpio_request(RK29_PIN2_PC4, NULL);
+ gpio_request(RK29_PIN2_PC3, NULL);
+ gpio_request(RK29_PIN2_PC2, NULL);
+ gpio_request(RK29_PIN2_PC1, NULL);
+ gpio_request(RK29_PIN2_PC0, NULL);
+}
+static void gpio_set_free(void)
+{
+ gpio_free(RK29_PIN6_PA0);
+ gpio_free(RK29_PIN6_PA1);
+ gpio_free(RK29_PIN6_PA2);
+ gpio_free(RK29_PIN6_PA3);
+ gpio_free(RK29_PIN6_PA4);
+ gpio_free(RK29_PIN6_PA5);
+ gpio_free(RK29_PIN6_PA6);
+
+ gpio_free(RK29_PIN2_PA5);
+ gpio_free(RK29_PIN2_PA4);
+ gpio_free(RK29_PIN2_PB0);
+ gpio_free(RK29_PIN2_PB1);
+ gpio_free(RK29_PIN2_PB2);
+ gpio_free(RK29_PIN2_PB3);
+
+ gpio_free(RK29_PIN1_PA4);
+ gpio_free(RK29_PIN1_PA3);
+
+ gpio_free(RK29_PIN2_PC7);
+ gpio_free(RK29_PIN2_PC6);
+ gpio_free(RK29_PIN2_PC5);
+ gpio_free(RK29_PIN2_PC4);
+ gpio_free(RK29_PIN2_PC3);
+ gpio_free(RK29_PIN2_PC2);
+ gpio_free(RK29_PIN2_PC1);
+ gpio_free(RK29_PIN2_PC0);
+}
+
+static void rk29_keygpio_suspend(void)
+{
+ gpio_pull_updown(RK29_PIN6_PA0, 0);
+ gpio_pull_updown(RK29_PIN6_PA1, 0);
+ gpio_pull_updown(RK29_PIN6_PA2, 0);
+ gpio_pull_updown(RK29_PIN6_PA3, 0);
+ gpio_pull_updown(RK29_PIN6_PA4, 0);
+ gpio_pull_updown(RK29_PIN6_PA5, 0);
+ gpio_pull_updown(RK29_PIN6_PA6, 0);//key pullup/pulldown disable
+
+ gpio_pull_updown(RK29_PIN2_PA4, 0);
+ gpio_pull_updown(RK29_PIN2_PA5, 0);
+ gpio_pull_updown(RK29_PIN2_PB0, 0);
+ gpio_pull_updown(RK29_PIN2_PB1, 0);
+ gpio_pull_updown(RK29_PIN2_PB2, 0);
+ gpio_pull_updown(RK29_PIN2_PB3, 0);
+}
+
+static void rk29_keygpio_resume(void)
+{
+ gpio_pull_updown(RK29_PIN6_PA0, 1);
+ gpio_pull_updown(RK29_PIN6_PA1, 1);
+ gpio_pull_updown(RK29_PIN6_PA2, 1);
+ gpio_pull_updown(RK29_PIN6_PA3, 1);
+ gpio_pull_updown(RK29_PIN6_PA4, 1);
+ gpio_pull_updown(RK29_PIN6_PA5, 1);
+ gpio_pull_updown(RK29_PIN6_PA6, 1);//key pullup/pulldown enable
+
+ gpio_pull_updown(RK29_PIN2_PA4, 1);
+ gpio_pull_updown(RK29_PIN2_PA5, 1);
+ gpio_pull_updown(RK29_PIN2_PB0, 1);
+ gpio_pull_updown(RK29_PIN2_PB1, 1);
+ gpio_pull_updown(RK29_PIN2_PB2, 1);
+ gpio_pull_updown(RK29_PIN2_PB3, 1);
+}
+
+static void spi_gpio_suspend(void)
+{
+ rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_GPIO1A4); //set iomux is gpio mode
+ rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_GPIO1A3);
+
+ rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_GPIO2C7);
+ rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_GPIO2C6);
+ //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_GPIO2C5);
+ rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME,GPIO2H_GPIO2C4);
+ rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_GPIO2C3);
+ rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_GPIO2C2);
+ rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_GPIO2C1);
+ rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_GPIO2C0);
+
+ gpio_direction_input(RK29_PIN1_PA4); //set gpio is input
+ gpio_direction_input(RK29_PIN1_PA3);
+ gpio_direction_input(RK29_PIN2_PC7);
+ gpio_direction_input(RK29_PIN2_PC6);
+ // gpio_direction_input(RK29_PIN2_PC5);
+ gpio_direction_input(RK29_PIN2_PC4);
+ gpio_direction_input(RK29_PIN2_PC3);
+ gpio_direction_input(RK29_PIN2_PC2);
+ gpio_direction_input(RK29_PIN2_PC1);
+ gpio_direction_input(RK29_PIN2_PC0);
+
+ gpio_pull_updown(RK29_PIN1_PA4, 0); //set gpio pullup/down disable
+ gpio_pull_updown(RK29_PIN1_PA3, 0);
+
+ gpio_pull_updown(RK29_PIN2_PC7, 0);
+ gpio_pull_updown(RK29_PIN2_PC6, 0);
+ //gpio_pull_updown(RK29_PIN2_PC5, 0);
+ gpio_pull_updown(RK29_PIN2_PC4, 0);
+ gpio_pull_updown(RK29_PIN2_PC3, 0);
+ gpio_pull_updown(RK29_PIN2_PC2, 0);
+ gpio_pull_updown(RK29_PIN2_PC1, 0);
+ gpio_pull_updown(RK29_PIN2_PC0, 0);
+}
+
+static void spi_gpio_resume(void)
+{
+ gpio_pull_updown(RK29_PIN1_PA4, 1); //set gpio pullup/down enable
+ gpio_pull_updown(RK29_PIN1_PA3, 1);
+
+ gpio_pull_updown(RK29_PIN2_PC7, 1);
+ gpio_pull_updown(RK29_PIN2_PC6, 1);
+ //gpio_pull_updown(RK29_PIN2_PC5, 1);
+ gpio_pull_updown(RK29_PIN2_PC4, 1);
+ gpio_pull_updown(RK29_PIN2_PC3, 1);
+ gpio_pull_updown(RK29_PIN2_PC2, 1);
+ gpio_pull_updown(RK29_PIN2_PC1, 1);
+ gpio_pull_updown(RK29_PIN2_PC0, 1);
+
+ rk29_mux_api_set(GPIO1A4_EMMCWRITEPRT_SPI0CS1_NAME,GPIO1L_SPI0_CSN1); //set iomux is spi mode
+ rk29_mux_api_set(GPIO1A3_EMMCDETECTN_SPI1CS1_NAME,GPIO1L_SPI1_CSN1);
+
+ rk29_mux_api_set(GPIO2C7_SPI1RXD_NAME,GPIO2H_SPI1_RXD);
+ rk29_mux_api_set(GPIO2C6_SPI1TXD_NAME,GPIO2H_SPI1_TXD);
+ //rk29_mux_api_set(GPIO2C5_SPI1CSN0_NAME,GPIO2H_SPI1_CSN0);
+ rk29_mux_api_set(GPIO2C4_SPI1CLK_NAME, GPIO2H_SPI1_CLK);
+ rk29_mux_api_set(GPIO2C3_SPI0RXD_NAME,GPIO2H_SPI0_RXD);
+ rk29_mux_api_set(GPIO2C2_SPI0TXD_NAME,GPIO2H_SPI0_TXD);
+ rk29_mux_api_set(GPIO2C1_SPI0CSN0_NAME,GPIO2H_SPI0_CSN0);
+ rk29_mux_api_set(GPIO2C0_SPI0CLK_NAME,GPIO2H_SPI0_CLK);
+}
+
+void rk29_setgpio_suspend_board(void)
+{
+ gpio_set_request();
+ rk29_keygpio_suspend();
+ spi_gpio_suspend();
+ gpio_set_free();
+}
+
+void rk29_setgpio_resume_board(void)
+{
+ gpio_set_request();
+ rk29_keygpio_resume();
+ spi_gpio_resume();
+ gpio_set_free();
+}
+#endif
#if defined(CONFIG_RK29_GPS)
* wm8994 codec
* author: qjb@rock-chips.com
*****************************************************************************************/
-//#if defined(CONFIG_MFD_WM8994)
-#if defined (CONFIG_REGULATOR_WM8994)
-static struct regulator_consumer_supply wm8994_ldo1_consumers[] = {
- {
- .supply = "DBVDD",
- },
- {
- .supply = "AVDD1",
- },
- {
- .supply = "CPVDD",
- },
- {
- .supply = "SPKVDD1",
- }
-};
-static struct regulator_consumer_supply wm8994_ldo2_consumers[] = {
- {
- .supply = "DCVDD",
- },
- {
- .supply = "AVDD2",
- },
- {
- .supply = "SPKVDD2",
- }
-};
-struct regulator_init_data regulator_init_data_ldo1 = {
- .constraints = {
- .name = "wm8994-ldo1",
- .min_uA = 00000,
- .max_uA = 18000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_ldo1_consumers),
- .consumer_supplies = wm8994_ldo1_consumers,
-};
-struct regulator_init_data regulator_init_data_ldo2 = {
- .constraints = {
- .name = "wm8994-ldo2",
- .min_uA = 00000,
- .max_uA = 18000,
- .always_on = true,
- .apply_uV = true,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_CURRENT,
- },
- .num_consumer_supplies = ARRAY_SIZE(wm8994_ldo2_consumers),
- .consumer_supplies = wm8994_ldo2_consumers,
-};
-#endif
-struct wm8994_drc_cfg wm8994_drc_cfg_pdata = {
- .name = "wm8994_DRC",
- .regs = {0,0,0,0,0},
-};
-
-struct wm8994_retune_mobile_cfg wm8994_retune_mobile_cfg_pdata = {
- .name = "wm8994_EQ",
- .rate = 0,
- .regs = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,},
-};
-
struct wm8994_pdata wm8994_platdata = {
-#if defined (CONFIG_GPIO_WM8994)
- .gpio_base = WM8994_GPIO_EXPANDER_BASE,
- //Fill value to initialize the GPIO
- .gpio_defaults ={},
-#endif
- //enable=0 disable ldo
-#if defined (CONFIG_REGULATOR_WM8994)
- .ldo = {
- {
- .enable = 0,
- //RK29_PIN5_PA1
- .supply = NULL,
- .init_data = ®ulator_init_data_ldo1,
- },
- {
- .enable = 0,
- .supply = NULL,
- .init_data = ®ulator_init_data_ldo2,
- }
- },
-#endif
- //DRC 0--use default
- .num_drc_cfgs = 0,
- .drc_cfgs = &wm8994_drc_cfg_pdata,
- //EQ 0--use default
- .num_retune_mobile_cfgs = 0,
- .retune_mobile_cfgs = &wm8994_retune_mobile_cfg_pdata,
-
- .lineout1_diff = 1,
- .lineout2_diff = 1,
-
- .lineout1fb = 1,
- .lineout2fb = 1,
+
+ .BB_input_diff = 0,
+ .BB_class = NO_PCM_BB,
- .micbias1_lvl = 1,
- .micbias2_lvl = 1,
+ .no_earpiece = 0,
+ .sp_hp_same_channel = 0,
- .jd_scthr = 0,
- .jd_thr = 0,
-
.PA_control_pin = 0,
.Power_EN_Pin = RK29_PIN5_PA1,
.headset_normal_vol = -6,
.BT_incall_vol = 0,
.BT_incall_mic_vol = 0,
- .recorder_vol = 20,
+ .recorder_vol = 30,
};
-//#endif
+
#ifdef CONFIG_RK_HEADSET_DET
#define HEADSET_GPIO RK29_PIN4_PD2
static void __init rk29_board_iomux_init(void)
{
int err;
+
+#ifdef CONFIG_UART1_RK29
+ //disable uart1 pull down
+ rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_GPIO2A5);
+ rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_GPIO2A4);
+
+ gpio_request(RK29_PIN2_PA5, NULL);
+ gpio_request(RK29_PIN2_PA4, NULL);
+
+ gpio_pull_updown(RK29_PIN2_PA5, PullDisable);
+ gpio_pull_updown(RK29_PIN2_PA4, PullDisable);
+
+ rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
+ rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
+
+ gpio_free(RK29_PIN2_PA5);
+ gpio_free(RK29_PIN2_PA4);
+#endif
#ifdef CONFIG_RK29_PWM_REGULATOR
rk29_mux_api_set(REGULATOR_PWM_MUX_NAME,REGULATOR_PWM_MUX_MODE);
#endif
{
mi->nr_banks = 1;
mi->bank[0].start = RK29_SDRAM_PHYS;
- mi->bank[0].node = PHYS_TO_NID(RK29_SDRAM_PHYS);
mi->bank[0].size = LINUX_SIZE;
#if SDRAM_SIZE > SZ_512M
mi->nr_banks = 2;
projects / firefly-linux-kernel-4.4.55.git / blobdiff