ARM: OMAP4: Enhance support for DPLLs with 4X multiplier

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index aa56c3e5bb34bd6be92d7a715796f071efa26dde..44ef54fa118b618ee9d335192e9badaabce54663 100644 (file)
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -124,6 +124,8 @@ static struct dpll_data dpll_abe_dd = {
        .enable_mask    = OMAP4430_DPLL_EN_MASK,
        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+       .m4xen_mask     = OMAP4430_DPLL_REGM4XEN_MASK,
+       .lpmode_mask    = OMAP4430_DPLL_LPMODE_EN_MASK,
        .max_multiplier = 2047,
        .max_divider    = 128,
        .min_divider    = 1,
@@ -365,6 +367,15 @@ static struct dpll_data dpll_iva_dd = {
 
 static struct clk dpll_iva_ck;
 
+static const struct clk_ops dpll_ck_ops = {
+       .enable         = &omap3_noncore_dpll_enable,
+       .disable        = &omap3_noncore_dpll_disable,
+       .recalc_rate    = &omap3_dpll_recalc,
+       .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_noncore_dpll_set_rate,
+       .get_parent     = &omap2_init_dpll_parent,
+};
+
 static struct clk_hw_omap dpll_iva_ck_hw = {
        .hw = {
                .clk = &dpll_iva_ck,
@@ -373,7 +384,7 @@ static struct clk_hw_omap dpll_iva_ck_hw = {
        .ops            = &clkhwops_omap3_dpll,
 };
 
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_ck_ops);
 
 static const char *dpll_iva_x2_ck_parents[] = {
        "dpll_iva_ck",
@@ -426,7 +437,7 @@ static struct clk_hw_omap dpll_mpu_ck_hw = {
        .ops            = &clkhwops_omap3_dpll,
 };
 
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_ck_ops);
 
 DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
 
@@ -475,7 +486,7 @@ static struct clk_hw_omap dpll_per_ck_hw = {
        .ops            = &clkhwops_omap3_dpll,
 };
 
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ck_ops);
 
 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
                   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
@@ -569,7 +580,7 @@ static struct clk_hw_omap dpll_usb_ck_hw = {
        .ops            = &clkhwops_omap3_dpll,
 };
 
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_ck_ops);
 
 static const char *dpll_usb_clkdcoldo_ck_parents[] = {
        "dpll_usb_ck",
@@ -1935,10 +1946,10 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-       CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-       CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-       CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-       CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+       CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };