ARM: OMAP4: clock: Lock PLLs in the right sequence

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a474334df7589fc866bbf37fbd645258b00..1d5b5290d2af3db91f5d57b0a9c945a2ccaa2e28 100644 (file)
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1706,6 +1706,18 @@ int __init omap4xxx_clk_init(void)
 
        omap2_clk_disable_autoidle_all();
 
+       /*
+        * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
+        * when its in bypass. So always lock USB before ABE DPLL.
+        */
+       /*
+        * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+        * domain can transition to retention state when not in use.
+        */
+       rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
        /*
         * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
         * state when turning the ABE clock domain. Workaround this by
@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
        if (rc)
                pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
-       /*
-        * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-        * domain can transition to retention state when not in use.
-        */
-       rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-       if (rc)
-               pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
        return 0;
 }