Merge branch 'rk_develop-3.10' into rk_develop-3.10-next

[firefly-linux-kernel-4.4.55.git] / arch / arm / kernel / setup.c

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 860952438bd31d1e293f5bf72d322822a39e19cc..e0ae7b52f4f0d8aa95dc04e65b0df7b4994b24e7 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -262,6 +262,19 @@ static int cpu_has_aliasing_icache(unsigned int arch)
        int aliasing_icache;
        unsigned int id_reg, num_sets, line_size;
 
+#ifdef CONFIG_BIG_LITTLE
+       /*
+        * We expect a combination of Cortex-A15 and Cortex-A7 cores.
+        * A7 = VIPT aliasing I-cache
+        * A15 = PIPT (non-aliasing) I-cache
+        * To cater for this discrepancy, let's assume aliasing I-cache
+        * all the time.  This means unneeded extra work on the A15 but
+        * only ptrace is affected which is not performance critical.
+        */
+       if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0)
+               return 1;
+#endif
+
        /* PIPT caches never alias. */
        if (icache_is_pipt())
                return 0;
@@ -531,6 +544,7 @@ void __init dump_machine_table(void)
 int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
 {
        struct membank *bank = &meminfo.bank[meminfo.nr_banks];
+       u64 aligned_start;
 
        if (meminfo.nr_banks >= NR_BANKS) {
                printk(KERN_CRIT "NR_BANKS too low, "
@@ -543,10 +557,16 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
         * Size is appropriately rounded down, start is rounded up.
         */
        size -= start & ~PAGE_MASK;
-       bank->start = PAGE_ALIGN(start);
+       aligned_start = PAGE_ALIGN(start);
+
+#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
+       if (aligned_start > ULONG_MAX) {
+               printk(KERN_CRIT "Ignoring memory at 0x%08llx outside "
+                      "32-bit physical address space\n", (long long)start);
+               return -EINVAL;
+       }
 
-#ifndef CONFIG_ARM_LPAE
-       if (bank->start + size < bank->start) {
+       if (aligned_start + size > ULONG_MAX) {
                printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
                        "32-bit physical address space\n", (long long)start);
                /*
@@ -554,10 +574,25 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
                 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
                 * This means we lose a page after masking.
                 */
-               size = ULONG_MAX - bank->start;
+               size = ULONG_MAX - aligned_start;
        }
 #endif
 
+       if (aligned_start < PHYS_OFFSET) {
+               if (aligned_start + size <= PHYS_OFFSET) {
+                       pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
+                               aligned_start, aligned_start + size);
+                       return -EINVAL;
+               }
+
+               pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
+                       aligned_start, (u64)PHYS_OFFSET);
+
+               size -= PHYS_OFFSET - aligned_start;
+               aligned_start = PHYS_OFFSET;
+       }
+
+       bank->start = aligned_start;
        bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
 
        /*
@@ -800,10 +835,12 @@ void __init setup_arch(char **cmdline_p)
        psci_init();
 #ifdef CONFIG_SMP
        if (is_smp()) {
-               if (psci_smp_available())
-                       smp_set_ops(&psci_smp_ops);
-               else if (mdesc->smp)
-                       smp_set_ops(mdesc->smp);
+               if (!mdesc->smp_init || !mdesc->smp_init()) {
+                       if (psci_smp_available())
+                               smp_set_ops(&psci_smp_ops);
+                       else if (mdesc->smp)
+                               smp_set_ops(mdesc->smp);
+               }
                smp_init_cpus();
        }
 #endif
@@ -877,6 +914,9 @@ static const char *hwcap_str[] = {
        "vfpv4",
        "idiva",
        "idivt",
+       "vfpd32",
+       "lpae",
+       "evtstrm",
        NULL
 };
 
@@ -885,6 +925,10 @@ static int c_show(struct seq_file *m, void *v)
        int i, j;
        u32 cpuid;
 
+#ifdef CONFIG_ARCH_ROCKCHIP
+       seq_printf(m, "Processor\t: %s rev %d (%s)\n",
+                  cpu_name, read_cpuid_id() & 15, elf_platform);
+#endif
        for_each_online_cpu(i) {
                /*
                 * glibc reads /proc/cpuinfo to determine the number of