Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / tegra124.dtsi

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 01a9f742b08f4fe2bf3a4184dbf34dd46dd7ccf9..1e204a6de12c3a4156821a289a2f7064bd346574 100644 (file)
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/tegra124-car.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
 
 #include "skeleton.dtsi"
@@ -188,6 +189,9 @@
                clock-names = "gpu", "pwr";
                resets = <&tegra_car 184>;
                reset-names = "gpu";
+
+               iommus = <&mc TEGRA_SWGROUP_GPU>;
+
                status = "disabled";
        };
 
@@ -254,6 +258,7 @@
                gpio-controller;
                #interrupt-cells = <2>;
                interrupt-controller;
+               gpio-ranges = <&pinmux 0 0 251>;
        };
 
        apbdma: dma@0,60020000 {
@@ -702,6 +707,30 @@
                #thermal-sensor-cells = <1>;
        };
 
+       dfll: clock@0,70110000 {
+               compatible = "nvidia,tegra124-dfll";
+               reg = <0 0x70110000 0 0x100>, /* DFLL control */
+                     <0 0x70110000 0 0x100>, /* I2C output control */
+                     <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+                     <0 0x70110200 0 0x100>; /* Look-up table RAM */
+               interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
+                        <&tegra_car TEGRA124_CLK_DFLL_REF>,
+                        <&tegra_car TEGRA124_CLK_I2C5>;
+               clock-names = "soc", "ref", "i2c";
+               resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
+               reset-names = "dvco";
+               #clock-cells = <0>;
+               clock-output-names = "dfllCPU_out";
+               nvidia,sample-rate = <12500>;
+               nvidia,droop-ctrl = <0x00000f00>;
+               nvidia,force-mode = <1>;
+               nvidia,cf = <10>;
+               nvidia,ci = <0>;
+               nvidia,cg = <2>;
+               status = "disabled";
+       };
+
        ahub@0,70300000 {
                compatible = "nvidia,tegra124-ahub";
                reg = <0x0 0x70300000 0x0 0x200>,
@@ -922,6 +951,15 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
+
+                       clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
+                                <&tegra_car TEGRA124_CLK_CCLK_LP>,
+                                <&tegra_car TEGRA124_CLK_PLL_X>,
+                                <&tegra_car TEGRA124_CLK_PLL_P>,
+                                <&dfll>;
+                       clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+                       /* FIXME: what's the actual transition time? */
+                       clock-latency = <300000>;
                };
 
                cpu@1 {
@@ -943,6 +981,18 @@
                };
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&{/cpus/cpu@0}>,
+                                    <&{/cpus/cpu@1}>,
+                                    <&{/cpus/cpu@2}>,
+                                    <&{/cpus/cpu@3}>;
+       };
+
        thermal-zones {
                cpu {
                        polling-delay-passive = <1000>;