};
vio1_isp_w0 {
reg = <0xffad0100 0x20>;
+ rockchip,priority = <2 2>;
};
vio1_isp_w1 {
reg = <0xffad0180 0x20>;
reg = <0xff800000 0x100>;
clocks = <&pclk_pd_alive>;
clock-names = "pclk_wdt";
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,irq = <0>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,irq = <1>;
rockchip,timeout = <60>;
rockchip,atboot = <1>;
rockchip,debug = <0>;
};
};
+ reset: reset@ff7601b8{
+ compatible = "rockchip,reset";
+ reg = <0xff7601b8 0x30>;
+ rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
+ #reset-cells = <1>;
+ };
+
nandc0: nandc@0xff400000 {
compatible = "rockchip,rk-nandc";
reg = <0xff400000 0x4000>;
nandc_id = <0>;
clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
- status = "okay";
};
nandc1: nandc@0xff410000 {
nandc_id = <1>;
clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
- status = "okay";
+ };
+
+ nandc0reg: nandc0@0xff400000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0xff400000 0x4000>;
};
emmc: rksdmmc@ff0f0000 {
num-cs = <2>;
clocks =<&clk_spi0>, <&clk_gates6 4>;
clock-names = "spi","pclk_spi0";
- //dmas = <&pdma1 11>, <&pdma1 12>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 11>, <&pdma1 12>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
num-cs = <1>;
clocks = <&clk_spi1>, <&clk_gates6 5>;
clock-names = "spi","pclk_spi1";
- //dmas = <&pdma1 13>, <&pdma1 14>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 13>, <&pdma1 14>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
num-cs = <2>;
clocks = <&clk_spi2>, <&clk_gates6 6>;
clock-names = "spi","pclk_spi2";
- //dmas = <&pdma1 15>, <&pdma1 16>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 15>, <&pdma1 16>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
status = "disabled";
};
- clocks-init{
+ rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
<&clk_edp 200000000>, <&clk_isp 200000000>,
<&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
<&clk_tspout 80000000>, <&clk_mac 125000000>;
+ rockchip,clocks-uboot-has-init =
+ <&aclk_vio0>;
};
clocks-enable {
compatible = "rockchip,clocks-enable";
clocks =
+ /*PLL*/
+ <&clk_dpll>, <&clk_gpll>,
+
/*PD_CORE*/
<&clk_gates0 2>, <&clk_core0>,
<&clk_core1>, <&clk_core2>,
/*PD_BUS*/
<&aclk_bus>, <&clk_gates0 3>,
<&hclk_bus>, <&pclk_bus>,
- <&clk_gates13 8>, <&clk_crypto>,
+ <&clk_gates13 8>,
<&clk_gates0 7>,
/*TIMER*/
<&clk_gates10 12>,/*aclk_dma1*/
<&clk_gates10 13>,/*aclk_strc_sys*/
<&clk_gates10 4>,/*aclk_intmem*/
- <&clk_gates11 6>,/*aclk_crypto*/
- <&clk_gates11 8>,/*aclk_ccp*/
/*hclk_bus*/
- <&clk_gates11 7>,/*hclk_crypto*/
<&clk_gates10 9>,/*hclk_rom*/
/*pclk_bus*/
<&clk_gates17 2>,/*pclk_pmu_niu*/
<&clk_gates17 3>,/*pclk_sgrf*/
- /*hclk_vio*/
- <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
- <&clk_gates15 10>,/*hclk_vio_niu*/
- <&clk_gates16 10>,/*hclk_vio2_h2p*/
- <&clk_gates16 11>,/*pclk_vio2_h2p*/
-
- /*aclk_vio0*/
- <&clk_gates15 11>,/*aclk_vio0_niu*/
-
- /*aclk_vio1*/
- <&clk_gates15 12>,/*aclk_vio1_niu*/
-
- /*HDMI*/
- //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
-
/*UART*/
<&clk_gates11 9>,/*pclk_uart2*/
pinctrl-0 = <&i2c1_sda &i2c1_scl>;
pinctrl-1 = <&i2c1_gpio>;
gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates10 3>;
+ clocks = <&clk_gates6 13>;
rockchip,check-idle = <1>;
status = "disabled";
};
pinctrl-0 = <&i2c2_sda &i2c2_scl>;
pinctrl-1 = <&i2c2_gpio>;
gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates6 13>;
+ clocks = <&clk_gates10 3>;
rockchip,check-idle = <1>;
status = "disabled";
};
compatible = "rockchip,rk3288-hdmi";
reg = <0xff980000 0x20000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default", "gpio";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_sda &i2c5_scl>;
pinctrl-1 = <&i2c5_gpio>;
clocks = <&clk_gates16 9>, <&clk_gates5 12>;
status = "disabled";
};
- lcdc1: lcdc@ff940000 {
+ lcdc0: lcdc@ff930000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <PRMRY>;
- rochchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- reg = <0xff940000 0x10000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,pwr18 = <0>;
+ rockchip,iommu-enabled = <0>;
+ reg = <0xff930000 0x10000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
- clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
+ clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
- lcdc0: lcdc@ff930000 {
+ lcdc1: lcdc@ff940000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <EXTEND>;
rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- reg = <0xff930000 0x10000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- //pinctrl-names = "default", "gpio";
- //pinctrl-0 = <&lcdc0_lcdc>;
- //pinctrl-1 = <&lcdc0_gpio>;
+ rockchip,iommu-enabled = <0>;
+ reg = <0xff940000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
- clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
+ clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
};
rga@ff920000 {
- compatible = "rockchip,rga";
+ compatible = "rockchip,rk3288-rga2";
reg = <0xff920000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
compatible = "rockchip-spdif";
reg = <0xff8b0000 0x10000>; //8channel
//reg = <ff880000 0x10000>;//2channel
- clocks = <&clk_spdif>, <&clk_spdif_8ch>;
- clock-names = "spdif_mclk","spdif_8ch_mclk";
+ clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
+ clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 3>;
//dmas = <&pdma0 2>; //2channel
};
dvfs {
- temp-limit-enable = <1>;
- target-temp = <80>;
vd_arm: vd_arm {
regulator_name = "vdd_arm";
816000 1100000
1008000 1100000
>;
- temp-channel = <1>;
+ channel = <0>;
+ temp-limit-enable = <1>;
+ target-temp = <80>;
normal-temp-limit = <
/*delta-temp delta-freq*/
3 96000
>;
performance-temp-limit = <
/*temp freq*/
- 110 816000
+ 100 816000
>;
status = "okay";
+ regu-mode-table = <
+ /*freq mode*/
+ 1008000 4
+ 0 3
+ >;
+ regu-mode-en = <0>;
};
};
};
300000 1200000
400000 1200000
>;
+ channel = <2>;
status = "disabled";
};
};
300000 1200000
400000 1200000
>;
+ channel = <1>;
status = "okay";
+ regu-mode-table = <
+ /*freq mode*/
+ 200000 4
+ 0 3
+ >;
+ regu-mode-en = <0>;
};
};
};
#address-cells = <1>;
#size-cells = <0>;
- rockchip,ion-heap@1 { /* CMA HEAP */
- compatible = "rockchip,ion-reserve";
- rockchip,ion_heap = <1>;
- reg = <0x00000000 0x20000000>; /* 512MB */
+ ion_drm: rockchip,ion-heap@5 {
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <5>;
+ reg = <0x00000000 0x00000000>;
+ };
+ ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <4>;
+ reg = <0x00000000 0x28000000>; /* 640MB */
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
- rockchip,ion_heap = <3>;
+ rockchip,ion-heap@0 { /* VMALLOC HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <0>;
};
};
vpu: vpu_service@ff9a0000 {
compatible = "vpu_service";
+ iommu_enabled = <0>;
reg = <0xff9a0000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
clocks = <&clk_vdpu>, <&hclk_vdpu>;
clock-names = "aclk_vcodec", "hclk_vcodec";
name = "vpu_service";
+ dev_mode = <0>;
//status = "disabled";
};
hevc: hevc_service@ff9c0000 {
compatible = "rockchip,hevc_service";
+ iommu_enabled = <0>;
reg = <0xff9c0000 0x800>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
+ dev_mode = <1>;
name = "hevc_service";
//status = "disabled";
};
iep: iep@ff900000 {
compatible = "rockchip,iep";
+ iommu_enabled = <0>;
reg = <0xff900000 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates15 2>, <&clk_gates15 3>;
compatible = "synopsys,phy";
/* offset bit mask */
rk_usb,bvalid = <0x288 14 1>;
+ rk_usb,iddig = <0x288 17 1>;
rk_usb,dcdenb = <0x328 14 1>;
rk_usb,vdatsrcenb = <0x328 7 1>;
rk_usb,vdatdetenb = <0x328 6 1>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 4>, <&clk_gates7 4>;
clock-names = "clk_usbphy0", "hclk_usb0";
+ resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
+ <&reset RK3288_SOFT_RST_USBOTGC>;
+ reset-names = "otg_ahb", "otg_phy", "otg_controller";
/*0 - Normal, 1 - Force Host, 2 - Force Device*/
rockchip,usb-mode = <0>;
};
<&usbphy_480m>;
clock-names = "clk_usbphy1", "hclk_usb1",
"usbphy_480m";
+ resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
+ <&reset RK3288_SOFT_RST_USBHOST1C>;
+ reset-names = "host1_ahb", "host1_phy", "host1_controller";
};
usb2: usb@ff500000 {
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 5>, <&clk_gates7 6>;
clock-names = "clk_usbphy2", "hclk_usb2";
+ resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
+ <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
+ reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
};
usb3: usb@ff520000 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 5>, <&clk_gates7 6>;
clock-names = "clk_usbphy3", "hclk_usb3";
+ status = "disabled";
};
hsic: hsic@ff5c0000 {
clock-names = "hsicphy_480m", "hclk_hsic",
"hsicphy_12m", "usbphy_480m",
"hsic_usbphy1", "hsic_usbphy2";
+ resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
+ <&reset RK3288_SOFT_RST_HSICPHY>;
+ reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
};
gmac: eth@ff290000 {
- compatible = "rockchip,gmac";
+ compatible = "rockchip,rk3288-gmac";
reg = <0xff290000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
interrupt-names = "macirq";
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
- //phy-mode = "rmii";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
iep_mmu {
dbgname = "iep";
- compatible = "iommu,iep_mmu";
+ compatible = "rockchip,iep_mmu";
reg = <0xff900800 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
vip_mmu {
dbgname = "vip";
- compatible = "iommu,vip_mmu";
+ compatible = "rockchip,vip_mmu";
reg = <0xff950800 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vip_mmu";
vopb_mmu {
dbgname = "vopb";
- compatible = "iommu,vopb_mmu";
+ compatible = "rockchip,vopb_mmu";
reg = <0xff930300 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
vopl_mmu {
dbgname = "vopl";
- compatible = "iommu,vopl_mmu";
+ compatible = "rockchip,vopl_mmu";
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
hevc_mmu {
dbgname = "hevc";
- compatible = "iommu,hevc_mmu";
- reg = <0xff9c0440 0x100>,
- <0xff9c0480 0x100>;
+ compatible = "rockchip,hevc_mmu";
+ reg = <0xff9c0440 0x40>,
+ <0xff9c0480 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
};
vpu_mmu {
dbgname = "vpu";
- compatible = "iommu,vpu_mmu";
+ compatible = "rockchip,vpu_mmu";
reg = <0xff9a0800 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
isp_mmu {
dbgname = "isp_mmu";
- compatible = "iommu,isp_mmu";
+ compatible = "rockchip,isp_mmu";
reg = <0xff914000 0x100>,
<0xff915000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|RKPM_CTR_PWR_DMNS
|RKPM_CTR_GTCLKS
|RKPM_CTR_PLLS
+ // |RKPM_CTR_GPIOS
// |RKPM_CTR_SYSCLK_DIV
// |RKPM_CTR_IDLEAUTO_MD
// |RKPM_CTR_ARMOFF_LPMD
|RKPM_CTR_ARMOFF_LOGDP_LPMD
)
>;
- rockchip,pmic-gpios = <
- RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
- RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
+ rockchip,pmic-suspend_gpios = <
+ RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
+ >;
+ rockchip,pmic-resume_gpios = <
+ RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
>;
+
};
isp: isp@ff910000{
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
- pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl";
+ pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
pinctrl-0 = <&isp_mipi>;
pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
- pinctrl-5 = <&isp_mipi &isp_flash_trigger>;
- pinctrl-6 = <&isp_mipi &isp_flash_trigger &isp_prelight>;
+ pinctrl-5 = <&isp_mipi>;
+ pinctrl-6 = <&isp_mipi &isp_prelight>;
+ pinctrl-7 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-8 = <&isp_flash_trigger>;
rockchip,isp,mipiphy = <2>;
rockchip,isp,cifphy = <1>;
rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
+ rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu_enable = <1>;
status = "okay";
};
+ cif: cif@ff950000 {
+ compatible = "rockchip,cif";
+ reg = <0xff950000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
+ clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out";
+ pinctrl-names = "cif_pin_all";
+ pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
+ status = "okay";
+ };
tsadc: tsadc@ff280000 {
compatible = "rockchip,tsadc";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
io-channel-ranges;
- clock-frequency = <50000>;
+ clock-frequency = <10000>;
clocks = <&clk_tsadc>, <&clk_gates7 2>;
clock-names = "tsadc", "pclk_tsadc";
+ pinctrl-names = "default", "tsadc_int";
+ pinctrl-0 = <&tsadc_gpio>;
+ pinctrl-1 = <&tsadc_int>;
+ tsadc-ht-temp = <120>;
+ tsadc-ht-reset-cru = <1>;
+ tsadc-ht-pull-gpio = <0>;
status = "okay";
};
pinctrl-1 = <&sdcard_vcc_18>;
pinctrl-2 = <&sdcard_vcc_33>;
};
+
+ chosen {
+ bootargs = "vmalloc=496M";
+ };
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff