num-cs = <2>;
clocks =<&clk_spi0>, <&clk_gates6 4>;
clock-names = "spi","pclk_spi0";
- //dmas = <&pdma1 11>, <&pdma1 12>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 11>, <&pdma1 12>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
num-cs = <1>;
clocks = <&clk_spi1>, <&clk_gates6 5>;
clock-names = "spi","pclk_spi1";
- //dmas = <&pdma1 13>, <&pdma1 14>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 13>, <&pdma1 14>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
num-cs = <2>;
clocks = <&clk_spi2>, <&clk_gates6 6>;
clock-names = "spi","pclk_spi2";
- //dmas = <&pdma1 15>, <&pdma1 16>;
- //#dma-cells = <2>;
- //dma-names = "tx", "rx";
+ dmas = <&pdma1 15>, <&pdma1 16>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
status = "disabled";
};
#address-cells = <1>;
#size-cells = <0>;
- ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
+ ion_drm: rockchip,ion-heap@5 {
compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <1>;
- reg = <0x00000000 0x20000000>; /* 512MB */
+ rockchip,ion_heap = <5>;
+ reg = <0x00000000 0x00000000>;
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
+ ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <3>;
+ rockchip,ion_heap = <4>;
+ reg = <0x00000000 0x28000000>; /* 640MB */
+ };
+ rockchip,ion-heap@0 { /* VMALLOC HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <0>;
};
};
clocks = <&clk_vdpu>, <&hclk_vdpu>;
clock-names = "aclk_vcodec", "hclk_vcodec";
name = "vpu_service";
+ dev_mode = <0>;
//status = "disabled";
};
interrupt-names = "irq_dec";
clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
+ dev_mode = <1>;
name = "hevc_service";
//status = "disabled";
};
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 5>, <&clk_gates7 6>;
clock-names = "clk_usbphy3", "hclk_usb3";
+ status = "disabled";
};
hsic: hsic@ff5c0000 {
rockchip,isp,iommu_enable = <1>;
status = "okay";
};
+ cif: cif@ff950000 {
+ compatible = "rockchip,cif";
+ reg = <0xff950000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
+ clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out";
+ pinctrl-names = "cif_pin_all";
+ pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
+ status = "okay";
+ };
tsadc: tsadc@ff280000 {
compatible = "rockchip,tsadc";