ARM: dts: rockchip: enable usb host2 for evb rk3288

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk3288-evb.dtsi

diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 32ccc86af502260b28cc731ae597dcc1e38911c2..cb5c8d8c1852fd5ab7d330781c00391e5d2e07eb 100644 (file)
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -111,6 +111,13 @@
                status = "disabled";
        };
 
+       ext_gmac: external-gmac-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <125000000>;
+               clock-output-names = "ext_gmac";
+               #clock-cells = <0>;
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
@@ -164,6 +171,16 @@
                regulator-boot-on;
        };
 
+       /* This switch DIO3222 HOST_DP_HOST to host2 (dwc2) */
+       vcc_3g: vcc-3g-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwr_3g>;
+               regulator-name = "vcc_3g";
+       };
+
        /*
         * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
         * vcc_io directly.  Those boards won't be able to power cycle SD cards
@@ -212,6 +229,22 @@
        vqmmc-supply = <&vccio_sd>;
 };
 
+&gmac {
+       phy-supply = <&vcc_phy>;
+       phy-mode = "rgmii";
+       clock_in_out = "input";
+       snps,reset-gpio = <&gpio4 7 0>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 1000000>;
+       assigned-clocks = <&cru SCLK_MAC>;
+       assigned-clock-parents = <&ext_gmac>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       tx_delay = <0x30>;
+       rx_delay = <0x10>;
+       status = "ok";
+};
+
 &edp_phy {
        status = "okay";
 };
@@ -336,6 +369,10 @@
                host_vbus_drv: host-vbus-drv {
                        rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
                };
+
+               pwr_3g: pwr-3g {
+                       rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
        };
 
        eth_phy {