#clock-cells = <0>;
};
- dummy_480m: dummy_480m {
+ dummy_cpll: dummy_cpll {
compatible = "rockchip,rk-fixed-clock";
- clock-output-names = "dummy_480m";
+ clock-output-names = "dummy_cpll";
clock-frequency = <0>;
#clock-cells = <0>;
};
compatible = "rockchip,rk-fixed-clock";
#clock-cells = <0>;
clock-output-names = "gmac_clkin";
- clock-frequency = <0>;
+ clock-frequency = <125000000>;
};
clk_hsadc_ext: clk_hsadc_ext {
#clock-cells = <0>;
};
+ pd_edp: pd_edp {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_edp";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_vop0: pd_vop0 {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_vop0";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_vop1: pd_vop1 {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_vop1";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_isp: pd_isp {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_isp";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_iep: pd_iep {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_iep";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_rga: pd_rga {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_rga";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_mipicsi: pd_mipicsi {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_mipicsi";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_mipidsi: pd_mipidsi {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_mipidsi";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_lvds: pd_lvds {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_lvds";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_hdmi: pd_hdmi {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_hdmi";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
};
status-reg = <0x0284 7>;
clocks = <&xin24m>;
clock-output-names = "clk_cpll";
- rockchip,pll-type = <CLK_PLL_3188PLUS>;
+ rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_bus_src: aclk_bus_src_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
/*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
clock-output-names = "aclk_bus_src";
#clock-cells = <0>;
clk_i2s_pll: i2s_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_i2s_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_spdif_pll: spdif_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spdif_pll";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
clk_isp: clk_isp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_isp";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_isp_jpe: clk_isp_jpe_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_isp_jpe";
#clock-cells = <0>;
#clock-init-cells = <1>;
aclk_peri: aclk_peri_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "aclk_peri";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_sdmmc: clk_sdmmc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdmmc";
#clock-cells = <0>;
};
- hsicphy_12m_div: hsicphy_12m_div {
+ ehci1phy_12m_div: ehci1phy_12m_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
- clocks = <&hsicphy_480m>;
- clock-output-names = "hsicphy_12m_div";
+ clocks = <&ehci1phy_480m>;
+ clock-output-names = "ehci1phy_12m_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
clk_sdio0: clk_sdio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio0";
#clock-cells = <0>;
};
clk_emmc: clk_emmc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_emmc";
#clock-cells = <0>;
};
usbphy_480m: usbphy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <11 2>;
- clocks = <&otgphy0_480m>, <&otgphy1_480m>, <&otgphy2_480m>;
+ clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>;
clock-output-names = "usbphy_480m";
#clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_USB480M>;
+ #clock-init-cells = <1>;
};
clk_uart0_pll: clk_uart0_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_uart0_pll";
#clock-cells = <0>;
};
uart_pll_mux: uart_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "uart_pll_mux";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_mac_pll: clk_mac_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
- clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>;
+ clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_mac_pll";
#clock-cells = <0>;
};
clk_hsadc_pll: clk_hsadc_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_hsadc_pll";
#clock-cells = <0>;
};
clk_spi0: clk_spi0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi0";
#clock-cells = <0>;
};
clk_spi1: clk_spi1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi1";
#clock-cells = <0>;
};
clk_cif_pll: clk_cif_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_cif_pll";
#clock-cells = <0>;
};
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
- <CLKOPS_RATE_MUX_EVENDIV>;
+ <CLKOPS_RATE_RK3288_DCLK_LCDC0>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_edp: clk_edp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_edp";
#clock-cells = <0>;
#clock-init-cells = <1>;
hclk_vio: hclk_vio_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
- clocks = <&aclk_vio0>;
+ clocks = <&clk_gates15 11>;
clock-output-names = "hclk_vio";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#address-cells = <1>;
#size-cells = <1>;
- hsicphy_480m: hsicphy_480m_mux {
+ ehci1phy_480m: ehci1phy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
- clock-output-names = "hsicphy_480m";
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
+ clock-output-names = "ehci1phy_480m";
#clock-cells = <0>;
};
- hsicphy_12m: hsicphy_12m_mux {
+ ehci1phy_12m: ehci1phy_12m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
- clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
- clock-output-names = "hsicphy_12m";
+ clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
+ clock-output-names = "ehci1phy_12m";
#clock-cells = <0>;
};
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
- <CLKOPS_RATE_MUX_DIV>;
+ <CLKOPS_RATE_RK3288_DCLK_LCDC1>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[5]: reserved */
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
- clocks = <&clk_cpll>, <&clk_gpll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
- clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
+ clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
- <&hsicphy_480m>, <&clk_cif_pll>,
+ <&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
- "hsicphy_480m", "clk_cif_pll",
+ "ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
- "g_pclk_uart4", "g_pclk_i2c2",
+ "g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
- "g_hclk_hsic", "g_hclk_usb_peri",
+ "g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
- "g_pclk_i2c0", "g_pclk_i2c1",
+ "g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
- <&pclk_dbg_src>, <&clk_gates12 8>,
- <&clk_gates12 8>, <&clk_gates12 8>,
+ <&pclk_dbg_src>, <&pclk_dbg_src>,
+ <&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
- "pclk_dbg_src", "reserved", /*"g_dbg_core_clk",*/
- "reserved", "reserved", /*"g_cs_dbg_clk", "g_pclk_core_niu",*/
+ "pclk_dbg_src", "g_dbg_core_clk",
+ "g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
- "g_clk_c2c_host", "g_clk_hsic_12m",
+ "g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
- rockchip,suspend-clkgating-setting=<0x1801 0x1801>;
+ rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
- <&aclk_vio0>, <&hclk_vio>,
+ <&clk_gates15 11>, <&hclk_vio>,
- <&dummy>, <&aclk_vio0>,
- <&hclk_vio>, <&aclk_vio1>,
+ <&dummy>, <&clk_gates15 11>,
+ <&hclk_vio>, <&clk_gates15 12>,
- <&hclk_vio>, <&hclk_vio>,
- <&hclk_vio>, <&aclk_vio0>,
+ <&hclk_vio>, <&dummy>,
+ <&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
- <&aclk_vio0>, <&hclk_vio>;
+ <&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
- "reserved", /*"g_aclk_rga",*/ "g_hclk_rga",
+ "reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
- "g_hclk_lcdc1", "g_h_vio_ahb",
- "g_hclk_vio_niu", "g_aclk_vio0_niu",
+ "g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
+ "reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
- "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu",*/
+ "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
- <&aclk_vio1>, <&pclkin_isp>,
+ <&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
- <&hclk_vio>, <&hclk_vio>,
+ <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
- "g_hclk_vio2_h2p", "g_pclk_vio2_h2p",
+ "reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
projects / firefly-linux-kernel-4.4.55.git / blobdiff