Merge branch 'linux-linaro-lsk-v4.4-android' of git://git.linaro.org/kernel/linux...

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk3288-clocks.dtsi

diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi
index 4a82c89af06f754a44480edec8307cb804524fc8..ce6d3395e83c9719c6daacce16b25f2a91bd0ff4 100755 (executable)
--- a/arch/arm/boot/dts/rk3288-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3288-clocks.dtsi
@@ -84,7 +84,7 @@
                                compatible = "rockchip,rk-fixed-clock";
                                #clock-cells = <0>;
                                clock-output-names = "gmac_clkin";
-                               clock-frequency = <0>;
+                               clock-frequency = <125000000>;
                        };
 
                        clk_hsadc_ext: clk_hsadc_ext {
@@ -862,11 +862,11 @@
                                                #clock-cells = <0>;
                                        };
 
-                                       hsicphy_12m_div: hsicphy_12m_div {
+                                       ehci1phy_12m_div: ehci1phy_12m_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <8 6>;
-                                               clocks = <&hsicphy_480m>;
-                                               clock-output-names = "hsicphy_12m_div";
+                                               clocks = <&ehci1phy_480m>;
+                                               clock-output-names = "ehci1phy_12m_div";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                        };
@@ -1459,7 +1459,7 @@
                                        hclk_vio: hclk_vio_div {
                                                compatible = "rockchip,rk3188-div-con";
                                                rockchip,bits = <8 5>;
-                                               clocks = <&aclk_vio0>;
+                                               clocks = <&clk_gates15 11>;
                                                clock-output-names = "hclk_vio";
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
@@ -1483,19 +1483,19 @@
                                        #address-cells = <1>;
                                        #size-cells = <1>;
 
-                                       hsicphy_480m: hsicphy_480m_mux {
+                                       ehci1phy_480m: ehci1phy_480m_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <0 2>;
                                                clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
-                                               clock-output-names = "hsicphy_480m";
+                                               clock-output-names = "ehci1phy_480m";
                                                #clock-cells = <0>;
                                        };
 
-                                       hsicphy_12m: hsicphy_12m_mux {
+                                       ehci1phy_12m: ehci1phy_12m_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <2 1>;
-                                               clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
-                                               clock-output-names = "hsicphy_12m";
+                                               clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
+                                               clock-output-names = "ehci1phy_12m";
                                                #clock-cells = <0>;
                                        };
 
@@ -2003,6 +2003,7 @@
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
                                                        <CLKOPS_RATE_MUX_DIV>;
+                                               rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
                                        };
 
                                        /* reg[13]: reserved */
@@ -2093,6 +2094,7 @@
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
                                                        <CLKOPS_RATE_MUX_DIV>;
+                                               rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
                                        };
 
                                        /* reg[5]: reserved */
@@ -2115,6 +2117,7 @@
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
                                                        <CLKOPS_RATE_MUX_DIV>;
+                                               rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
                                        };
 
                                        /* reg[13]: reserved */
@@ -2246,7 +2249,7 @@
                                                <&aclk_vio1>,           <&dclk_lcdc1>,
 
                                                <&clk_rga>,                     <&aclk_rga>,
-                                               <&hsicphy_480m>,                <&clk_cif_pll>,
+                                               <&ehci1phy_480m>,               <&clk_cif_pll>,
 
                                                <&dummy>,               <&clk_vepu>,
                                                <&dummy>,               <&clk_vdpu>,
@@ -2259,7 +2262,7 @@
                                                "aclk_vio1",            "dclk_lcdc1",
 
                                                "clk_rga",              "aclk_rga",
-                                               "hsicphy_480m",         "clk_cif_pll",
+                                               "ehci1phy_480m",                "clk_cif_pll",
 
                                                /*Not use hclk_vpu_gate tmp, fixme*/
                                                "reserved",             "clk_vepu",
@@ -2365,7 +2368,7 @@
                                                "g_pclk_uart0",         "g_pclk_uart1",
                                                "reserved",             "g_pclk_uart3",
 
-                                               "g_pclk_uart4",         "g_pclk_i2c2",
+                                               "g_pclk_uart4",         "g_pclk_i2c1",
                                                "g_pclk_i2c3",          "g_pclk_i2c4";
                                             rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
 
@@ -2395,7 +2398,7 @@
                                                "g_hclk_otg0",          "g_pmu_hclk_otg0",
                                                "g_hclk_host0",         "g_hclk_host1",
 
-                                               "g_hclk_hsic",          "g_hclk_usb_peri",
+                                               "g_hclk_ehci1",         "g_hclk_usb_peri",
                                                "g_hp_ahb_arbi",                "g_aclk_peri_niu",
 
                                                "g_h_emem_peri",                "g_hclk_mem_peri",
@@ -2489,7 +2492,7 @@
 
                                        clock-output-names =
                                                "g_pclk_pwm",           "g_pclk_timer",
-                                               "g_pclk_i2c0",          "g_pclk_i2c1",
+                                               "g_pclk_i2c0",          "g_pclk_i2c2",
 
                                                "g_aclk_intmem",                "g_clk_intmem0",
                                                "g_clk_intmem1",                "g_clk_intmem2",
@@ -2595,7 +2598,7 @@
                                                "clk_otgphy0",          "clk_otgphy1",
                                                "clk_otgphy2",          "clk_otg_adp",
 
-                                               "g_clk_c2c_host",               "g_clk_hsic_12m",
+                                               "g_clk_c2c_host",               "g_clk_ehci1_12m",
                                                "g_clk_lcdc_pwm0",              "g_clk_lcdc_pwm1",
 
                                                "g_clk_wifi",           "aclk_hevc",
@@ -2635,7 +2638,7 @@
                                                "reserved",             "reserved";
                                                 //rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
                                                 
-                                                rockchip,suspend-clkgating-setting=<0x1801 0x1801>;
+                                                rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
 
                                        #clock-cells = <1>;
                                };
@@ -2645,28 +2648,28 @@
                                        reg = <0x019c 0x4>;
                                        clocks =
                                                <&aclk_rga>,            <&hclk_vio>,
-                                               <&aclk_vio0>,           <&hclk_vio>,
+                                               <&clk_gates15 11>,      <&hclk_vio>,
 
-                                               <&dummy>,               <&aclk_vio0>,
-                                               <&hclk_vio>,            <&aclk_vio1>,
+                                               <&dummy>,               <&clk_gates15 11>,
+                                               <&hclk_vio>,            <&clk_gates15 12>,
 
-                                               <&hclk_vio>,            <&hclk_vio>,
-                                               <&hclk_vio>,            <&aclk_vio0>,
+                                               <&hclk_vio>,            <&dummy>,
+                                               <&dummy>,               <&aclk_vio0>,
 
                                                <&aclk_vio1>,           <&aclk_rga>,
-                                               <&aclk_vio0>,           <&hclk_vio>;
+                                               <&clk_gates15 11>,      <&hclk_vio>;
 
                                        clock-output-names =
-                                               "reserved", /*"g_aclk_rga",*/   "g_hclk_rga",
+                                               "reserved", /*"g_aclk_rga"*/    "g_hclk_rga",
                                                "g_aclk_iep",           "g_hclk_iep",
 
                                                "g_aclk_lcdc_iep",              "g_aclk_lcdc0",
                                                "g_hclk_lcdc0",         "g_aclk_lcdc1",
 
-                                               "g_hclk_lcdc1",         "g_h_vio_ahb",
-                                               "g_hclk_vio_niu",               "g_aclk_vio0_niu",
+                                               "g_hclk_lcdc1",         "reserved", /* "g_h_vio_ahb" */
+                                               "reserved",/*"g_hclk_vio_niu"*/         "g_aclk_vio0_niu",
 
-                                               "g_aclk_vio1_niu",              "reserved",/*"g_aclk_rga_niu",*/
+                                               "g_aclk_vio1_niu",              "reserved",/*"g_aclk_rga_niu"*/
                                                "g_aclk_vip",           "g_hclk_vip";
                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
 
@@ -2678,13 +2681,13 @@
                                        reg = <0x01a0 0x4>;
                                        clocks =
                                                <&pclkin_cif>,          <&hclk_vio>,
-                                               <&aclk_vio1>,           <&pclkin_isp>,
+                                               <&clk_gates15 12>,      <&pclkin_isp>,
 
                                                <&hclk_vio>,            <&hclk_vio>,
                                                <&hclk_vio>,            <&hclk_vio>,
 
                                                <&hclk_vio>,            <&hclk_vio>,
-                                               <&hclk_vio>,            <&hclk_vio>,
+                                               <&dummy>,               <&dummy>,
 
                                                <&dummy>,               <&dummy>,
                                                <&dummy>,               <&dummy>;
@@ -2697,7 +2700,7 @@
                                                "g_p_mipi_csi",         "g_pclk_lvds_phy",
 
                                                "g_pclk_edp_ctrl",              "g_p_hdmi_ctrl",
-                                               "g_hclk_vio2_h2p",              "g_pclk_vio2_h2p",
+                                               "reserved",             "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
 
                                                "reserved",             "reserved",
                                                "reserved",             "reserved";