ARM: dts: rockchip: add Cortex-A9 SPI controller nodes

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk3188.dtsi

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ee801a9c6b74144e4a8153908a5e1ad07365bfef..573ef6129fb4755e942c61c45ad3fa890a24f77b 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -206,6 +206,42 @@
                        };
                };
 
+               spi0 {
+                       spi0_clk: spi0-clk {
+                               rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_cs0: spi0-cs0 {
+                               rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_tx: spi0-tx {
+                               rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_rx: spi0-rx {
+                               rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_cs1: spi0-cs1 {
+                               rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               spi1 {
+                       spi1_clk: spi1-clk {
+                               rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi1_cs0: spi1-cs0 {
+                               rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi1_rx: spi1-rx {
+                               rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi1_tx: spi1-tx {
+                               rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi1_cs1: spi1-cs1 {
+                               rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
                uart0 {
                        uart0_xfer: uart0-xfer {
                                rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
@@ -381,6 +417,18 @@
        pinctrl-0 = <&pwm3_out>;
 };
 
+&spi0 {
+       compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+};
+
+&spi1 {
+       compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_xfer>;