-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/ddr.h>
+#include <dt-bindings/rkfb/rk_fb.h>
+#include <dt-bindings/suspend/rockchip-pm.h>
+#include <dt-bindings/sensor-dev.h>
#include "skeleton.dtsi"
+#include "rk3188-pinctrl.dtsi"
+#include "rk3188-clocks.dtsi"
/ {
compatible = "rockchip,rk3188";
interrupt-parent = <&gic>;
+ rockchip,sram = <&sram>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ lcdc0 = &lcdc0;
+ lcdc1 = &lcdc1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
cpus {
#address-cells = <1>;
};
L2: cache-controller@10138000 {
- compatible = "arm,pl310-cache";
+ compatible = "rockchip,pl310-cache", "arm,pl310-cache";
reg = <0x10138000 0x1000>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <1 1 1>;
- arm,data-latency = <2 3 1>;
- prefetch-ctrl = <0x70000003>;
+ arm,data-latency = <3 1 2>;
+ rockchip,prefetch-ctrl = <0x70000003>;
/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
- power-ctrl = <0x3>;
+ rockchip,power-ctrl = <0x3>;
/*
(0x1 << 0) | // Full line of write zero behavior Enabled
(0x1 << 25) | // Round-robin replacement
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
*/
- aux-ctrl = <0x72000001 (~0x72000001)>;
+ rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
};
- cpu_axi_bus: cpu_axi_bus@10128000 {
+ cpu_axi_bus: cpu_axi_bus {
compatible = "rockchip,cpu_axi_bus";
- reg = <0x10128000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
qos {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
dmac {
- offset = <0x1000>;
- priority = <0 0>;
+ reg = <0x10129000 0x20>;
+ rockchip,priority = <0 0>;
};
cpu0 {
- offset = <0x2000>;
- priority = <0 0>;
+ reg = <0x1012a000 0x20>;
+ rockchip,priority = <0 0>;
};
- cpu1r {
- offset = <0x2080>;
- priority = <0 0>;
+ cpu1_r {
+ reg = <0x1012a080 0x20>;
+ rockchip,priority = <0 0>;
};
- cpu1w {
- offset = <0x2100>;
- priority = <0 0>;
+ cpu1_w {
+ reg = <0x1012a100 0x20>;
+ rockchip,priority = <0 0>;
};
peri {
- offset = <0x4000>;
- priority = <2 2>;
+ reg = <0x1012c000 0x20>;
+ rockchip,priority = <2 2>;
};
gpu {
- offset = <0x5000>;
- priority = <2 1>;
+ reg = <0x1012d000 0x20>;
+ rockchip,priority = <2 1>;
};
vpu {
- offset = <0x6000>;
+ reg = <0x1012e000 0x20>;
};
vop0 {
- offset = <0x7000>;
- priority = <3 3>;
+ reg = <0x1012f000 0x20>;
+ rockchip,priority = <3 3>;
};
cif0 {
- offset = <0x7080>;
+ reg = <0x1012f080 0x20>;
};
ipp {
- offset = <0x7100>;
+ reg = <0x1012f100 0x20>;
};
vop1 {
- offset = <0x7180>;
- priority = <3 3>;
+ reg = <0x1012f180 0x20>;
+ rockchip,priority = <3 3>;
};
cif1 {
- offset = <0x7200>;
+ reg = <0x1012f200 0x20>;
};
rga {
- offset = <0x7280>;
+ reg = <0x1012f280 0x20>;
+ };
+ };
+ msch {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ msch {
+ reg = <0x10128000 0x18>;
+ rockchip,read-latency = <0x3f>;
};
};
};
reg = <0x10080000 0x20>; /* 32 bytes */
};
- sram@10080020 {
+ sram: sram@10080020 {
compatible = "mmio-sram";
reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
map-exec;
reg = <0x20004000 0x4000>;
};
- timer@200380a0 {
- compatible = "rockchip,timer";
- reg = <0x200380a0 0x20>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- };
-
timer@20038000 {
compatible = "rockchip,timer";
reg = <0x20038000 0x20>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,percpu = <0>;
};
timer@20038020 {
compatible = "rockchip,timer";
reg = <0x20038020 0x20>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,percpu = <1>;
+ };
+
+ timer@20038040 {
+ compatible = "rockchip,timer";
+ reg = <0x20038040 0x20>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,percpu = <2>;
};
timer@20038060 {
compatible = "rockchip,timer";
reg = <0x20038060 0x20>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,percpu = <3>;
};
timer@20038080 {
compatible = "rockchip,timer";
reg = <0x20038080 0x20>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,broadcast = <1>;
+ };
+
+ timer@200380a0 {
+ compatible = "rockchip,timer";
+ reg = <0x200380a0 0x20>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,clocksource = <1>;
+ };
+
+ watchdog:wdt@2004c000 {
+ compatible = "rockchip,watch dog";
+ reg = <0x2004c000 0x100>;
+ clocks = <&clk_gates7 15>;
+ clock-names = "pclk_wdt";
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,irq = <1>;
+ rockchip,timeout = <5>;
+ rockchip,atboot = <1>;
+ rockchip,debug = <0>;
+ status = "disabled";
+ };
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@20018000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20018000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ };
+
+ pdma1: pdma@20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ };
+ };
+
+ emmc: rksdmmc@1021C000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x1021C000 0x4000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;/*irq=57*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ //pinctrl-names = "default",,"suspend";
+ //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
+ clocks = <&clk_gates2 14>;
+ num-slots = <1>;
+
+ fifo-depth = <0x80>;
+ bus-width = <4>;
+ };
+
+ sdmmc: rksdmmc@10214000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x10214000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; /*irq=55*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default","suspend";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
+ pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
+ clocks = <&clk_gates2 11>;
+ num-slots = <1>;
+
+ fifo-depth = <0x100>;
+ bus-width = <4>;
+ };
+
+ sdio: rksdmmc@10218000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x10218000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default","suspend";
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
+ clocks = <&clk_gates2 13>;
+ num-slots = <1>;
+
+ fifo-depth = <0x100>;
+ bus-width = <4>;
};
uart0: serial@10124000 {
reg = <0x10124000 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
+ clocks = <&clk_uart0>, <&clk_gates8 0>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
- id = <0>;
+ dmas = <&pdma0 0>, <&pdma0 1>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
};
reg = <0x10126000 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
+ clocks = <&clk_uart1>, <&clk_gates8 1>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
- id = <1>;
+ dmas = <&pdma0 2>, <&pdma0 3>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
status = "disabled";
};
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
+ clocks = <&clk_uart2>, <&clk_gates8 2>;
+ clock-names = "sclk_uart", "pclk_uart";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
- id = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
status = "disabled";
};
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
+ clocks = <&clk_uart3>, <&clk_gates8 3>;
+ clock-names = "sclk_uart", "pclk_uart";
reg-shift = <2>;
reg-io-width = <4>;
- id = <3>;
+ dmas = <&pdma1 8>, <&pdma1 9>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
+ status = "disabled";
+ };
+
+ fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,signal-irq = <112>;
+ rockchip,wake-irq = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@20070000 {
+ compatible = "rockchip,rockchip-spi";
+ reg = <0x20070000 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
+ rockchip,spi-src-clk = <0>;
+ num-cs = <2>;
+ clocks =<&clk_spi0>, <&clk_gates7 12>;
+ clock-names = "spi","pclk_spi0";
+ dmas = <&pdma1 10>, <&pdma1 11>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi1: spi@20074000 {
+ compatible = "rockchip,rockchip-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
+ rockchip,spi-src-clk = <1>;
+ num-cs = <2>;
+ clocks = <&clk_spi1>, <&clk_gates7 13>;
+ clock-names = "spi","pclk_spi1";
+ dmas = <&pdma1 12>, <&pdma1 13>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@2002d000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x2002d000 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_sda &i2c0_scl>;
+ pinctrl-1 = <&i2c0_gpio>;
+ gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 4>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2002f000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x2002f000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c1_sda &i2c1_scl>;
+ pinctrl-1 = <&i2c1_gpio>;
+ gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 5>;
+ rockchip,check-idle = <1>;
status = "disabled";
};
+
+ i2c2: i2c@20056000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_sda &i2c2_scl>;
+ pinctrl-1 = <&i2c2_gpio>;
+ gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 6>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2005a000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x2005a000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c3_sda &i2c3_scl>;
+ pinctrl-1 = <&i2c3_gpio>;
+ gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 7>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2005e000 {
+ compatible = "rockchip,rk30-i2c";
+ reg = <0x2005e000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_sda &i2c4_scl>;
+ pinctrl-1 = <&i2c4_gpio>;
+ gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates8 8>;
+ rockchip,check-idle = <1>;
+ status = "disabled";
+ };
+
+ clocks-init{
+ compatible = "rockchip,clocks-init";
+ rockchip,clocks-init-parent =
+ <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
+ <&aclk_peri &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
+ <&clk_uart_pll_mux &clk_gpll>;
+ rockchip,clocks-init-rate =
+ <&clk_core 792000000>, <&clk_gpll 768000000>,
+ <&clk_cpll 594000000>, <&aclk_cpu 192000000>,
+ <&hclk_cpu 96000000>, <&pclk_cpu 48000000>,
+ <&pclk_ahb2apb 48000000>, <&aclk_peri 192000000>,
+ <&hclk_peri 96000000>, <&pclk_peri 48000000>,
+ <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
+ <&aclk_lcdc1 300000000>;
+ };
+ rockchip_suspend {
+ //compatible = "rockchip,rkpm_suspend";
+ // define value is in dt-bindint/suspend/rockchip-pm.h
+ rockchip,ctrbits = <
+ (
+ RKPM_CTR_PWR_DMNS
+ |RKPM_CTR_GTCLKS
+ |RKPM_CTR_PLLS
+ |RKPM_CTR_SYSCLK_DIV
+ |RKPM_CTR_NORIDLE_MD
+ )
+ >;
+ rockchip,pmic-gpios=<
+ RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
+ RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
+ >;
+
+ };
+ fb: fb{
+ compatible = "rockchip,rk-fb";
+ rockchip,disp-mode = <DUAL>;
+ };
+
+ rk_screen: rk_screen{
+ compatible = "rockchip,screen";
+ };
+
+ nandc: nandc {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x10050000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ lcdc0:lcdc@1010c000 {
+ compatible = "rockchip,rk3188-lcdc";
+ rockchip,prop = <PRMRY>;
+ rochchip,pwr18 = <0>;
+ reg = <0x1010c000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lcdc1:lcdc@1010e000 {
+ compatible = "rockchip,rk3188-lcdc";
+ rockchip,prop = <EXTEND>;
+ rockchip,pwr18 = <0>;
+ reg = <0x1010e000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&lcdc1_lcdc>;
+ pinctrl-1 = <&lcdc1_gpio>;
+ status = "disabled";
+ };
+
+ rga@10114000 {
+ compatible = "rockchip,rga";
+ reg = <0x10114000 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates6 10>, <&clk_gates6 11>;
+ clock-names = "hclk_rga", "aclk_rga";
+ };
+
+ adc: adc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ rockchip,adc-vref = <1800>;
+ clock-frequency = <1000000>;
+ clocks = <&clk_saradc>, <&clk_gates7 14>;
+ clock-names = "saradc", "pclk_saradc";
+ status = "disabled";
+ };
+
+ spdif: rockchip-spdif@0x1011e000 {
+ compatible = "rockchip-spdif";
+ reg = <0x1011e000 0x2000>;
+ clocks = <&clk_spdif>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma0 8>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ };
+
+ i2s0: rockchip-i2s@0x1011a000 {
+ compatible = "rockchip-i2s";
+ reg = <0x1011a000 0x2000>;
+ i2s-id = <0>;
+ clocks = <&clk_i2s>;
+ clock-names = "i2s_clk";
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma0 6>,
+ <&pdma0 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
+ pinctrl-1 = <&i2s0_gpio>;
+ };
+
+ pwm0: pwm@20030000{
+ compatible = "rockchip,pwm";
+ reg = <0x20030000 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "disabled";
+
+ };
+
+ pwm1: pwm@20030010{
+ compatible = "rockchip,pwm";
+ reg = <0x20030010 0x10>; /*0x20030000*/
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ status = "disabled";
+
+ };
+ pwm2: pwm@20050020{
+ compatible = "rockchip,pwm";
+ reg = <0x20050020 0x10>; /*0x20030000*/
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ status = "disabled";
+
+ };
+
+ pwm3: pwm@20050030{
+ compatible = "rockchip,pwm";
+ reg = <0x20050030 0x10>; /*0x20030000*/
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ status = "disabled";
+
+ };
+ dvfs {
+ vd_cpu:
+ vd_cpu {
+ regulator_name="vdd_arm";
+ suspend_volt=<1000>; //mV
+ pd_a9 {
+ clk_core_dvfs_table:
+ clk_core {
+ operating-points = <
+ /* KHz uV */
+ 312000 900000
+ 504000 950000
+ 816000 1000000
+ 1008000 1100000
+ 1200000 1200000
+ 1416000 1300000
+ 1608000 1350000
+ >;
+ };
+ };
+ };
+
+ vd_core:
+ vd_core {
+ regulator_name="vdd_logic";
+ suspend_volt=<1000>; //mV
+
+ pd_gpu {
+ clk_gpu_dvfs_table:
+ clk_gpu {
+ operating-points = <
+ /* KHz uV */
+ 200000 1200000
+ 300000 1200000
+ 400000 1200000
+ >;
+ };
+ };
+
+ pd_ddr {
+ clk_ddr_dvfs_table:
+ clk_ddr {
+ operating-points = <
+ /* KHz uV */
+ 200000 1200000
+ 300000 1200000
+ 400000 1200000
+ >;
+ };
+ };
+ };
+ };
+ ion{
+ compatible = "rockchip,ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rockchip,ion-heap@1 { /* CMA HEAP */
+ compatible = "rockchip,ion-reserve";
+ reg = <1>;
+ memory-reservation = <0x00000000 0x10000000>; /* 256MB */
+ };
+ rockchip,ion-heap@3 { /* SYSTEM HEAP */
+ reg = <3>;
+ };
+ };
+
+ dwc_control_usb: dwc-control-usb@200080ac {
+ compatible = "rockchip,rk3188-dwc-control-usb";
+ reg = <0x200080ac 0x4>,
+ <0x2000810c 0x10>,
+ <0x2000811c 0x10>,
+ <0x2000812c 0x8>,
+ <0x20008138 0x8>;
+ reg-names = "GRF_SOC_STATUS0",
+ "GRF_UOC0_BASE",
+ "GRF_UOC1_BASE",
+ "GRF_UOC2_BASE",
+ "GRF_UOC3_BASE";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg_bvalid";
+ gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_gates4 5>;
+ clock-names = "hclk_usb_peri";
+
+ usb_bc{
+ compatible = "rockchip,ctrl";
+ rk_usb,bvalid = <0xac 10 1>;
+ rk_usb,line = <0xac 11 2>;
+ rk_usb,softctrl = <0x114 2 1>;
+ rk_usb,opmode = <0x118 1 2>;
+ rk_usb,xcvrsel = <0x118 3 2>;
+ rk_usb,termsel = <0x118 5 1>;
+ };
+ };
+
+
+ usb0: usb@10180000 {
+ compatible = "rockchip,rk3188_usb20_otg";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates1 5>, <&clk_gates5 13>;
+ clock-names = "clk_usbphy0", "hclk_usb0";
+ };
+
+ usb1: usb@101c0000 {
+ compatible = "rockchip,rk3188_usb20_host";
+ reg = <0x101c0000 0x40000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates1 6>, <&clk_gates7 3>;
+ clock-names = "clk_usbphy1", "hclk_usb1";
+ };
+
+ hsic: hsic@10240000 {
+ compatible = "rockchip,rk3188_rk_hsic_host";
+ reg = <0x10240000 0x40000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
+ <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
+ clock-names = "hsicphy_480m", "hclk_hsic",
+ "hsicphy_12m", "hsic_usbphy1";
+ };
+
+ vmac@10204000 {
+ compatible = "rockchip,vmac";
+ reg = <0x10204000 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
+ pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
+ };
+
+ ap0_vcc_domain: ap0-vcc-domain {
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&ap0_vcc >;
+ pinctrl-1 = <&ap0_vcc_18>;
+ pinctrl-2 = <&ap0_vcc_33>;
+ };
+ ap1_vcc_domain: ap1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&ap1_vcc >;
+ pinctrl-1 = <&ap1_vcc_18>;
+ pinctrl-2 = <&ap1_vcc_33>;
+ };
+ cif_vcc_domain: cif-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&cif_vcc>;
+ pinctrl-1 = <&cif_vcc_18>;
+ pinctrl-2 = <&cif_vcc_33>;
+ };
+ flash_vcc_domain: flash-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&flash_vcc>;
+ pinctrl-1 = <&flash_vcc_18>;
+ pinctrl-2 = <&flash_vcc_33>;
+ };
+ vccio0_vcc_domain: vccio0-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&vccio0_vcc>;
+ pinctrl-1 = <&vccio0_vcc_18>;
+ pinctrl-2 = <&vccio0_vcc_33>;
+ };
+ vccio1_vcc_domain: vccio1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&vccio1_vcc>;
+ pinctrl-1 = <&vccio1_vcc_18>;
+ pinctrl-2 = <&vccio1_vcc_33>;
+ };
+ lcdc0_vcc_domain: lcdc0-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&lcdc0_vcc>;
+ pinctrl-1 = <&lcdc0_vcc_18>;
+ pinctrl-2 = <&lcdc0_vcc_33>;
+ };
+ lcdc1_vcc_domain: lcdc1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&lcdc1_vcc>;
+ pinctrl-1 = <&lcdc1_vcc_18>;
+ pinctrl-2 = <&lcdc1_vcc_33>;
+ };
+
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff