i2c2 = &i2c2;
i2c3 = &i2c3;
lcdc = &lcdc;
- // spi0 = &spi0;
+ spi0 = &spi0;
};
cpus {
};
core {
reg = <0x1012a000 0x20>;
- rockchip,priority = <3 2>;
};
peri {
reg = <0x1012c000 0x20>;
};
vip {
reg = <0x1012f200 0x20>;
+ rockchip,priority = <3 3>;
};
};
};
};
- sram: sram@10080000 {
+ sram: sram@10080400 {
compatible = "mmio-sram";
- reg = <0x10080000 0x2000>;
+ reg = <0x10080400 0x1C00>;
map-exec;
+ map-cacheable;
};
timer {
pdma: pdma@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
+ clocks = <&clk_gates5 1>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
interrupt-names = "macirq";
clocks = <&clk_mac_ref>, <&clk_gates2 6>,
<&clk_gates2 7>, <&clk_gates2 4>,
- <&clk_gates2 5>,
+ <&clk_gates2 5>, <&clk_gates10 10>,
<&clk_gates10 11>;
clock-names = "clk_mac", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
- "clk_mac_refout",
+ "clk_mac_refout", "aclk_mac",
"pclk_mac";
- //phy-mode = "rmii";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
status = "disabled";
};
- clocks-init{
+ rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
<&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
<&clk_mac_pll &clk_cpll>;
rockchip,clocks-init-rate =
- <&clk_core 816000000>, <&clk_gpll 594000000>,
+ <&clk_core 600000000>, <&clk_gpll 594000000>,
<&clk_cpll 400000000>, <&aclk_cpu 300000000>,
<&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
<&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
<&clk_gates4 10>,/*aclk_strc_sys*/
/*hclk_cpu_pre*/
- <&clk_gates5 6>,/*hclk_rom*/
+ //<&clk_gates5 6>,/*hclk_rom*/
<&clk_gates3 5>,/*hclk_crypto*/
/*pclk_cpu_pre*/
<&clk_gates5 4>,/*pclk_grf*/
<&clk_gates5 7>,/*pclk_ddrupctl*/
- <&clk_gates5 14>,/*pclk_acodec*/
- <&clk_gates3 8>,/*pclk_hdmi*/
+ //<&clk_gates5 14>,/*pclk_acodec*/
+ //<&clk_gates3 8>,/*pclk_hdmi*/
/*aclk_peri_pre*/
- <&clk_gates10 10>,/*aclk_gmac*/
+ //<&clk_gates10 10>,/*aclk_gmac*/
<&clk_gates4 3>,/*aclk_peri_axi_matrix*/
- <&clk_gates5 1>,/*aclk_dmac2*/
+ //<&clk_gates5 1>,/*aclk_dmac2*/
<&clk_gates9 15>,/*aclk_peri_niu*/
+ <&clk_gates9 2>,/*g_pclk_pmu*/
+ <&clk_gates9 3>,/*g_pclk_pmu_noc*/
<&clk_gates4 2>,/*aclk_cpu_peri*/
/*hclk_peri_pre*/
<&clk_gates4 0>,/*hclk_peri_matrix*/
- <&clk_gates9 13>,/*hclk_usb_peri*/
+ //<&clk_gates9 13>,/*hclk_usb_peri*/
<&clk_gates9 14>,/*hclk_peri_arbi*/
/*pclk_peri_pre*/
<&clk_gates4 1>,/*pclk_peri_axi_matrix*/
/*hclk_vio_pre*/
- <&clk_gates6 12>,/*hclk_vio_niu*/
- <&clk_gates6 1>,/*hclk_lcdc*/
+ //<&clk_gates6 12>,/*hclk_vio_niu*/
+ //<&clk_gates6 1>,/*hclk_lcdc*/
/*aclk_vio0_pre*/
- <&clk_gates6 13>,/*aclk_vio*/
- <&clk_gates6 0>,/*aclk_lcdc*/
+ //<&clk_gates6 13>,/*aclk_vio*/
+ //<&clk_gates6 0>,/*aclk_lcdc*/
/*aclk_vio1_pre*/
- <&clk_gates9 10>,/*aclk_vio1_niu*/
+ //<&clk_gates9 10>,/*aclk_vio1_niu*/
/*UART*/
<&clk_gates1 12>,
<&clk_gates1 13>,
<&clk_gates8 2>,/*pclk_uart2*/
- <&clk_gpu>,
+ //<&clk_gpu>,
/*jtag*/
- <&clk_gates1 3>,/*clk_jtag*/
+ //<&clk_gates1 3>,/*clk_jtag*/
/*pmu*/
<&clk_gates1 0>;/*pclk_pmu_pre*/
status = "disabled";
};
- i2s0: i2s@10220000 {
+ i2s0: i2s0@10220000 {
compatible = "rockchip-i2s";
reg = <0x10220000 0x1000>;
i2s-id = <0>;
//pinctrl-names = "default", "sleep";
//pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
//pinctrl-1 = <&i2s0_gpio>;
+ status = "disabled";
};
- i2s1: i2s@10200000 {
+ i2s1: i2s1@10200000 {
compatible = "rockchip-i2s";
reg = <0x10200000 0x1000>;
i2s-id = <1>;
};
dsihost0: mipi@10110000{
- compatible = "rockchip,rk32-dsi";
+ compatible = "rockchip,rk312x-dsi";
rockchip,prop = <0>;
reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
+ clocks = <&clk_gates2 15>, <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>, <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
status = "okay";
};
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "idle";
+ pinctrl-names = "default", "idle", "udbg";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_gpio>;
+ pinctrl-2 = <&uart2_xfer>;
clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
clock-names = "clk_mmc", "hclk_mmc";
dmas = <&pdma 10>;
fifo-depth = <0x100>;
bus-width = <4>;
};
+
+ spi0: spi@20074000 {
+ compatible = "rockchip,rockchip-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
+ //pinctrl-0 = <&spi0_txd_mux1 &spi0_rxd_mux1 &spi0_clk_mux1 &spi0_cs0_mux1 &spi0_cs1_mux1>;
+ //pinctrl-0 = <&spi0_txd_mux2 &spi0_rxd_mux2 &spi0_clk_mux2 &spi0_cs0_mux2>;
+ rockchip,spi-src-clk = <0>;
+ num-cs = <2>;
+ clocks =<&clk_spi0>, <&clk_gates7 12>;
+ clock-names = "spi","pclk_spi0";
+ dmas = <&pdma 8>, <&pdma 9>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
adc: adc@2006c000 {
compatible = "rockchip,saradc";
pinctrl-0 = <&pwm3_pin>;
clocks = <&clk_gates7 10>;
clock-names = "pclk_pwm";
+ remote_pwm_id = <3>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
dwc_control_usb: dwc-control-usb@20008000 {
compatible = "rockchip,rk3126-dwc-control-usb";
reg = <0x20008000 0x4>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg_bvalid";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg_bvalid",
+ "otg0_linestate",
+ "otg1_linestate";
clocks = <&clk_gates9 13>;
clock-names = "hclk_usb_peri";
rockchip,remote_wakeup;
usb_bc{
compatible = "inno,phy";
regbase = &dwc_control_usb;
+ rk_usb,bvalid = <0x14c 5 1>;
+ rk_usb,iddig = <0x14c 8 1>;
+ rk_usb,vdmsrcen = <0x184 12 1>;
+ rk_usb,vdpsrcen = <0x184 11 1>;
+ rk_usb,rdmpden = <0x184 10 1>;
+ rk_usb,idpsrcen = <0x184 9 1>;
+ rk_usb,idmsinken = <0x184 8 1>;
+ rk_usb,idpsinken = <0x184 7 1>;
+ rk_usb,dpattach = <0x2c0 7 1>;
+ rk_usb,cpdet = <0x2c0 6 1>;
+ rk_usb,dcpattach = <0x2c0 5 1>;
};
};
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates1 5>, <&clk_gates5 13>;
clock-names = "clk_usbphy0", "hclk_usb0";
- resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
+ resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_UTMI0>,
<&reset RK3128_RST_OTGC0>;
reset-names = "otg_ahb", "otg_phy", "otg_controller";
/*0 - Normal, 1 - Force Host, 2 - Force Device*/
rockchip,usb-mode = <0>;
};
- usb1: usb@101c0000 {
- compatible = "rockchip,rk3126_usb20_host";
- reg = <0x101c0000 0x40000>;
+ ehci: usb@101c0000 {
+ compatible = "rockchip,rk3126_ehci";
+ reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates1 6>, <&clk_gates7 3>;
- clock-names = "clk_usbphy1", "hclk_usb1";
+ clock-names = "clk_usbphy1", "hclk_host0";
resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
<&reset RK3128_RST_OTGC1>;
reset-names = "host_ahb", "host_phy", "host_controller";
};
+ ohci: usb@101e0000 {
+ compatible = "rockchip,rk3126_ohci";
+ reg = <0x101e0000 0x20000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <ONE_DUAL>;
lvds: lvds@20038000 {
compatible = "rockchip,rk31xx-lvds";
- reg = <0x20038000 0x4000>;
- clocks = <&clk_gates5 0>;
- clock-names = "pclk_lvds";
+ reg = <0x20038000 0x4000>, <0x101100b0 0x01>;
+ reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+ clocks = <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>;
+ clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
+ status = "disabled";
};
lcdc: lcdc@1010e000 {
compatible = "rockchip,rk312x-lcdc";
rockchip,prop = <PRMRY>;
- reg = <0x1010e000 0x2000>;
+ reg = <0x1010e000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc";
+ clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
+ clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
rockchip,iommu-enabled = <1>;
status = "disabled";
};
pinctrl-names = "default", "gpio";
pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
pinctrl-1 = <&hdmi_gpio>;
- clocks = <&clk_gates3 8>;
- clock-names = "pclk_hdmi";
+ clocks = <&clk_gates3 8>, <&pd_hdmi>;
+ clock-names = "pclk_hdmi", "pd_hdmi";
+ rockchip,hdcp_enable = <0>;
+ rockchip,cec_enable = <0>;
status = "disabled";
};
status = "disabled";
};
- vpu: vpu_service@10106000 {
- compatible = "vpu_service";
+ vpu: vpu_service {
+ compatible = "rockchip,vpu_sub";
iommu_enabled = <1>;
reg = <0x10106000 0x800>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
- clocks = <&clk_vdpu>, <&hclk_vdpu>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
+ dev_mode = <0>;
name = "vpu_service";
- status = "okay";
};
- hevc: hevc_service@10104000 {
- compatible = "rockchip,hevc_service";
+ hevc: hevc_service {
+ compatible = "rockchip,hevc_sub";
iommu_enabled = <1>;
reg = <0x10104000 0x400>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
+ dev_mode = <1>;
+ name = "hevc_service";
+ };
+
+ vpu_combo: vpu_combo@ff9a0000 {
+ compatible = "rockchip,vpu_combo";
+ subcnt = <2>;
+ rockchip,sub = <&vpu>, <&hevc>;
clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- name = "hevc_service";
+ mode_bit = <15>;
+ mode_ctrl = <0x144>;
+ name = "vpu_combo";
status = "okay";
};
compatible = "rockchip,rk312x-rga";
reg = <0x1010c000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates0 11>, <&clk_gates1 4>;
+ clocks = <&clk_gates6 10>, <&clk_gates6 11>;
clock-names = "hclk_rga", "aclk_rga";
status = "okay";
};
vop_mmu {
dbgname = "vop";
- compatible = "iommu,vop_mmu";
+ compatible = "rockchip,vop_mmu";
reg = <0x1010e300 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
hevc_mmu {
dbgname = "hevc";
- compatible = "iommu,hevc_mmu";
- reg = <0x10104440 0x100>,
- <0x10104480 0x100>;
+ compatible = "rockchip,hevc_mmu";
+ reg = <0x10104440 0x40>,
+ <0x10104480 0x40>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
};
vpu_mmu {
dbgname = "vpu";
- compatible = "iommu,vpu_mmu";
- reg = <0x10104800 0x100>;
+ compatible = "rockchip,vpu_mmu";
+ reg = <0x10106800 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
};
iep_mmu {
dbgname = "iep";
- compatible = "iommu,iep_mmu";
+ compatible = "rockchip,iep_mmu";
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
};
dvfs {
- temp-limit-enable = <0>;
- target-temp = <80>;
-
vd_arm: vd_arm {
regulator_name = "vdd_arm";
pd_core {
816000 1100000
1008000 1100000
>;
+ temp-limit-enable = <0>;
+ target-temp = <80>;
temp-channel = <1>;
normal-temp-limit = <
/*delta-temp delta-freq*/
0 3
>;
regu-mode-en = <0>;
+ lkg_adjust_volt_en = <1>;
+ channel = <0>;
+ def_table_lkg = <35>;
+ min_adjust_freq = <1200000>;
+ lkg_adjust_volt_table = <
+ /*lkg(mA) volt(uV)*/
+ 60 25000
+ >;
};
};
};
#address-cells = <1>;
#size-cells = <0>;
- ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
- compatible = "rockchip,ion-reserve";
- rockchip,ion_heap = <1>;
- reg = <0x00000000 0x10000000>; /* 256MB */
+ ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <4>;
+ reg = <0x00000000 0x800000>; /* 8MB */
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
- rockchip,ion_heap = <3>;
+ rockchip,ion-heap@0 { /* VMALLOC HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <0>;
};
};
cif: cif@1010a000 {
compatible = "rockchip,cif";
reg = <0x1010a000 0x2000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates3 3>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
+ clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
status = "okay";
};
clocks = <&clk_gates5 14>;
clock-names = "g_pclk_acodec";
};
- rockchip-audio {
+ rockchip_audio: audio-rk312x {
compatible = "audio-rk312x";
dais {
dai0 {
projects / firefly-linux-kernel-4.4.55.git / blobdiff