i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
+ lcdc = &lcdc;
spi0 = &spi0;
};
<&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
<&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
rockchip,clocks-init-rate =
- <&clk_core 1000000000>, <&clk_gpll 594000000>,
+ <&clk_core 1200000000>, <&clk_gpll 1188000000>,
<&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
<&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
<&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
- <&clk_gpu 300000000>, <&aclk_vio_pre 300000000>,
+ <&clk_gpu 400000000>, <&aclk_vio_pre 300000000>,
<&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
<&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
<&clk_mac_ref_div 25000000>;
pinctrl-0 = <&pwm3_pin>;
clocks = <&clk_gates7 10>;
clock-names = "pclk_pwm";
+ remote_pwm_id = <3>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "idle";
+ pinctrl-names = "default", "idle", "udbg";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_gpio>;
+ pinctrl-2 = <&uart2_xfer>;
cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
clock-names = "clk_mmc", "hclk_mmc";
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <NO_DUAL>;
+ rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
};
rk_screen: rk_screen{
#address-cells = <1>;
#size-cells = <0>;
- ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
- compatible = "rockchip,ion-reserve";
- rockchip,ion_heap = <1>;
+ ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <4>;
reg = <0x00000000 0x00000000>; /* 0MB */
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
- rockchip,ion_heap = <3>;
+ rockchip,ion-heap@0 { /* VMALLOC HEAP */
+ compatible = "rockchip,ion-heap";
+ rockchip,ion_heap = <0>;
};
};
- vpu: vpu_service@10108000 {
+ /*vpu: vpu_service@10108000 {
compatible = "vpu_service";
iommu_enabled = <1>;
reg = <0x10108000 0x800>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
name = "hevc_service";
status = "okay";
+ };*/
+ vpu: vpu_service {
+ compatible = "rockchip,vpu_sub";
+ iommu_enabled = <1>;
+ reg = <0x10108400 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ dev_mode = <0>;
+ name = "vpu_service";
+ };
+
+ hevc: hevc_service {
+ compatible = "rockchip,hevc_sub";
+ iommu_enabled = <1>;
+ reg = <0x1010c000 0x400>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ dev_mode = <1>;
+ name = "hevc_service";
+ };
+
+ vpu_combo: vpu_combo@ff9a0000 {
+ compatible = "rockchip,vpu_combo";
+ subcnt = <2>;
+ rockchip,sub = <&vpu>, <&hevc>;
+ clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ mode_bit = <3>;
+ mode_ctrl = <0x144>;
+ name = "vpu_combo";
+ status = "okay";
};
vop_mmu {