ARM: dts: msm: Add SDHC controller nodes for MSM8974 and DB8074 board

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 23aa387450377a2fefa632b766a228e4b1a9bfb4..c530a33a10a0f8585368b2ed007c36aad7eacfc8 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -192,6 +192,28 @@
                        clock-names = "core", "iface";
                };
 
+               sdhci@f9824900 {
+                       compatible = "qcom,sdhci-msm-v4";
+                       reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                       reg-names = "hc_mem", "core_mem";
+                       interrupts = <0 123 0>, <0 138 0>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+                       clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       status = "disabled";
+               };
+
+               sdhci@f98a4900 {
+                       compatible = "qcom,sdhci-msm-v4";
+                       reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+                       reg-names = "hc_mem", "core_mem";
+                       interrupts = <0 125 0>, <0 221 0>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+                       clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       status = "disabled";
+               };
+
                rng@f9bff000 {
                        compatible = "qcom,prng";
                        reg = <0xf9bff000 0x200>;