Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64...

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0716525a77f41c602d219f2360bb0ab1f5..6c1511263a55deacd582b96bd4c57edad59300a8 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc0>;
                        qcom,saw = <&saw0>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@1 {
@@ -33,6 +34,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc1>;
                        qcom,saw = <&saw1>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@2 {
@@ -43,6 +45,7 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc2>;
                        qcom,saw = <&saw2>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                cpu@3 {
@@ -53,12 +56,23 @@
                        next-level-cache = <&L2>;
                        qcom,acc = <&acc3>;
                        qcom,saw = <&saw3>;
+                       cpu-idle-states = <&CPU_SPC>;
                };
 
                L2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                };
+
+               idle-states {
+                       CPU_SPC: spc {
+                               compatible = "qcom,idle-state-spc",
+                                               "arm,idle-state";
+                               entry-latency-us = <400>;
+                               exit-latency-us = <900>;
+                               min-residency-us = <3000>;
+                       };
+               };
        };
 
        cpu-pmu {
@@ -139,26 +153,26 @@
                        reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
                };
 
-               saw0: regulator@2089000 {
-                       compatible = "qcom,saw2";
+               saw0: power-controller@2089000 {
+                       compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
 
-               saw1: regulator@2099000 {
-                       compatible = "qcom,saw2";
+               saw1: power-controller@2099000 {
+                       compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
 
-               saw2: regulator@20a9000 {
-                       compatible = "qcom,saw2";
+               saw2: power-controller@20a9000 {
+                       compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
 
-               saw3: regulator@20b9000 {
-                       compatible = "qcom,saw2";
+               saw3: power-controller@20b9000 {
+                       compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
                        reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
                        regulator;
                };
@@ -166,6 +180,7 @@
                gsbi1: gsbi@12440000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <1>;
                        reg = <0x12440000 0x100>;
                        clocks = <&gcc GSBI1_H_CLK>;
                        clock-names = "iface";
@@ -173,6 +188,8 @@
                        #size-cells = <1>;
                        ranges;
 
+                       syscon-tcsr = <&tcsr>;
+
                        i2c1: i2c@12460000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x12460000 0x1000>;
@@ -187,6 +204,7 @@
                gsbi2: gsbi@12480000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <2>;
                        reg = <0x12480000 0x100>;
                        clocks = <&gcc GSBI2_H_CLK>;
                        clock-names = "iface";
@@ -194,6 +212,8 @@
                        #size-cells = <1>;
                        ranges;
 
+                       syscon-tcsr = <&tcsr>;
+
                        i2c2: i2c@124a0000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x124a0000 0x1000>;
@@ -208,6 +228,7 @@
                gsbi7: gsbi@16600000 {
                        status = "disabled";
                        compatible = "qcom,gsbi-v1.0.0";
+                       cell-index = <7>;
                        reg = <0x16600000 0x100>;
                        clocks = <&gcc GSBI7_H_CLK>;
                        clock-names = "iface";
@@ -215,6 +236,8 @@
                        #size-cells = <1>;
                        ranges;
 
+                       syscon-tcsr = <&tcsr>;
+
                        serial@16640000 {
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16640000 0x1000>,
@@ -239,6 +262,13 @@
                        #reset-cells = <1>;
                };
 
+               lcc: clock-controller@28000000 {
+                       compatible = "qcom,lcc-apq8064";
+                       reg = <0x28000000 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                mmcc: clock-controller@4000000 {
                        compatible = "qcom,mmcc-apq8064";
                        reg = <0x4000000 0x1000>;
@@ -349,5 +379,10 @@
                                pinctrl-0 = <&sdc4_gpios>;
                        };
                };
+
+               tcsr: syscon@1a400000 {
+                       compatible = "qcom,tcsr-apq8064", "syscon";
+                       reg = <0x1a400000 0x100>;
+               };
        };
 };