Merge tag 'md/3.12' of git://neil.brown.name/md

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / kirkwood-6282.dtsi

diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index a63a1113726274f8ff56060c7a6abe41dd01b2d9..3933a331ddc2ed8d8f71b58c4cc7389e7e860220 100644 (file)
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,4 +1,59 @@
 / {
+       mbus {
+               pcie-controller {
+                       compatible = "marvell,kirkwood-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
+                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 9>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 2>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 10>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 18>;
+                               status = "disabled";
+                       };
+               };
+       };
        ocp@f1000000 {
 
                pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@
                        status = "disabled";
                };
 
-               pcie-controller {
-                       compatible = "marvell,kirkwood-pcie";
-                       status = "disabled";
-                       device_type = "pci";
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-
-                       bus-range = <0x00 0xff>;
-
-                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                 0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
-                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                       pcie@1,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                               reg = <0x0800 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               #interrupt-cells = <1>;
-                               ranges;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &intc 9>;
-                               marvell,pcie-port = <0>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gate_clk 2>;
-                               status = "disabled";
-                       };
-
-                       pcie@2,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
-                               reg = <0x1000 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               #interrupt-cells = <1>;
-                               ranges;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &intc 10>;
-                               marvell,pcie-port = <1>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gate_clk 18>;
-                               status = "disabled";
-                       };
-               };
        };
 };