ARM: dts: imx: add "jedec,spi-nor" flash compatible binding

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / imx6qdl-sabrelite.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 782379320517735f7beb62814e0ce1944ecebb18..2f8510632f951da9f8d741c9a129443374970523 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -53,6 +53,17 @@
                        gpio = <&gpio3 22 0>;
                        enable-active-high;
                };
+
+               reg_can_xcvr: regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+                       regulator-name = "CAN XCVR";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_can_xcvr>;
+                       gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+               };
        };
 
        gpio-keys {
@@ -148,6 +159,20 @@
        status = "okay";
 };
 
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1>;
+       xceiver-supply = <&reg_can_xcvr>;
+       status = "okay";
+};
+
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
 &ecspi1 {
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio3 19 0>;
@@ -156,7 +181,7 @@
        status = "okay";
 
        flash: m25p80@0 {
-               compatible = "sst,sst25vf016b";
+               compatible = "sst,sst25vf016b", "jedec,spi-nor";
                spi-max-frequency = <20000000>;
                reg = <0>;
        };
@@ -239,6 +264,20 @@
                        >;
                };
 
+               pinctrl_can1: can1grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
+                               MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
+                       >;
+               };
+
+               pinctrl_can_xcvr: can-xcvrgrp {
+                       fsl,pins = <
+                               /* Flexcan XCVR enable */
+                               MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
+                       >;
+               };
+
                pinctrl_ecspi1: ecspi1grp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1