ARC: [axs101] Tweak DDR port aperture mappings for performance

[firefly-linux-kernel-4.4.55.git] / arch / arc / plat-axs10x / axs10x.c

diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 2e7686d1382f6f8194544ac6c54be757c45372b7..759a7a19889f29a2633d8b99e8aae5b3be471aba 100644 (file)
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -173,8 +173,8 @@ static const struct aperture axc001_memmap[16] = {
        {AXC001_SLV_NONE,               0x0},
        {AXC001_SLV_DDR_PORT0,          0x0}, /* 0x8000_0000: DDR   0..256M */
        {AXC001_SLV_DDR_PORT0,          0x1}, /* 0x9000_0000: DDR 256..512M */
-       {AXC001_SLV_DDR_PORT1,          0x0},
-       {AXC001_SLV_DDR_PORT1,          0x1},
+       {AXC001_SLV_DDR_PORT0,          0x2},
+       {AXC001_SLV_DDR_PORT0,          0x3},
        {AXC001_SLV_NONE,               0x0},
        {AXC001_SLV_AXI_TUNNEL,         0xD},
        {AXC001_SLV_AXI_TUNNEL,         0xE}, /* MB: CREG, CGU... */
@@ -194,10 +194,10 @@ static const struct aperture axc001_axi_tunnel_memmap[16] = {
        {AXC001_SLV_NONE,               0x0},
        {AXC001_SLV_NONE,               0x0},
        {AXC001_SLV_NONE,               0x0},
-       {AXC001_SLV_DDR_PORT0,          0x0},
-       {AXC001_SLV_DDR_PORT0,          0x1},
        {AXC001_SLV_DDR_PORT1,          0x0},
        {AXC001_SLV_DDR_PORT1,          0x1},
+       {AXC001_SLV_DDR_PORT1,          0x2},
+       {AXC001_SLV_DDR_PORT1,          0x3},
        {AXC001_SLV_NONE,               0x0},
        {AXC001_SLV_AXI_TUNNEL,         0xD},
        {AXC001_SLV_AXI_TUNNEL,         0xE},