thermal: rockchip: add rk3328 support

[firefly-linux-kernel-4.4.55.git] / Documentation / devicetree / bindings / phy / phy-miphy365x.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
index 42c880886cf74e2937156ce8fb3e0b93067e6ecc..8772900e056a06cd71579a2e6cf005993e38a472 100644 (file)
--- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -6,8 +6,10 @@ for SATA and PCIe.
 
 Required properties (controller (parent) node):
 - compatible    : Should be "st,miphy365x-phy"
-- st,syscfg     : Should be a phandle of the system configuration register group
-                 which contain the SATA, PCIe mode setting bits
+- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
+                 containing the miphy registers and integer array should contain
+                 an entry for each port sub-node, specifying the control
+                 register offset inside the sysconfig group.
 
 Required nodes :  A sub-node is required for each channel the controller
                   provides. Address range information including the usual
@@ -18,15 +20,14 @@ Required nodes      :  A sub-node is required for each channel the controller
 Required properties (port (child) node):
 - #phy-cells   : Should be 1 (See second example)
                  Cell after port phandle is device type from:
-                       - MIPHY_TYPE_SATA
-                       - MIPHY_TYPE_PCI
+                       - PHY_TYPE_SATA
+                       - PHY_TYPE_PCI
 - reg          : Address and length of register sets for each device in
                  "reg-names"
 - reg-names     : The names of the register addresses corresponding to the
                  registers filled in "reg":
                        - sata:   For SATA devices
                        - pcie:   For PCIe devices
-                       - syscfg: To specify the syscfg based config register
 
 Optional properties (port (child) node):
 - st,sata-gen       :  Generation of locally attached SATA IP. Expected values
@@ -39,20 +40,20 @@ Example:
 
        miphy365x_phy: miphy365x@fe382000 {
                compatible      = "st,miphy365x-phy";
-               st,syscfg       = <&syscfg_rear>;
+               st,syscfg       = <&syscfg_rear 0x824 0x828>;
                #address-cells  = <1>;
                #size-cells     = <1>;
                ranges;
 
                phy_port0: port@fe382000 {
-                       reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-                       reg-names = "sata", "pcie", "syscfg";
+                       reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+                       reg-names = "sata", "pcie";
                        #phy-cells = <1>;
                        st,sata-gen = <3>;
                };
 
                phy_port1: port@fe38a000 {
-                       reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
+                       reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
                        reg-names = "sata", "pcie", "syscfg";
                        #phy-cells = <1>;
                        st,pcie-tx-pol-inv;
@@ -67,10 +68,10 @@ property, containing a phandle to the phy port node and a device type.
 
 Example:
 
-#include <dt-bindings/phy/phy-miphy365x.h>
+#include <dt-bindings/phy/phy.h>
 
        sata0: sata@fe380000 {
                ...
-               phys      = <&phy_port0 MIPHY_TYPE_SATA>;
+               phys      = <&phy_port0 PHY_TYPE_SATA>;
                ...
        };