-
-/* A: clock inversion */
-#define SH_FSI_INVERSION_MASK 0x0000000F
-#define SH_FSI_LRM_INV (1 << 0)
-#define SH_FSI_BRM_INV (1 << 1)
-#define SH_FSI_LRS_INV (1 << 2)
-#define SH_FSI_BRS_INV (1 << 3)
-
-/* B: format mode */
-#define SH_FSI_FMT_MASK 0x000000F0
-#define SH_FSI_FMT_DAI (0 << 4)
-#define SH_FSI_FMT_SPDIF (1 << 4)
-
-/* C: chip specific */
-#define SH_FSI_OPTION_MASK 0x00000F00
-#define SH_FSI_ENABLE_STREAM_MODE (1 << 8) /* for 16bit data */
-
-/* D: clock selecter if master mode */
-#define SH_FSI_CLK_MASK 0x0000F000
-#define SH_FSI_CLK_EXTERNAL (0 << 12)
-#define SH_FSI_CLK_CPG (1 << 12) /* FSIxCK + FSI-DIV */
-
-/*
- * set_rate return value
- *
- * see ACKMD/BPFMD on
- * ACK_MD (FSI2)
- * CKG1 (FSI)
- *
- * err : return value < 0
- * no change : return value == 0
- * change xMD : return value > 0
- *
- * 0x-00000AB
- *
- * A: ACKMD value
- * B: BPFMD value
- */
-
-#define SH_FSI_ACKMD_MASK (0xF << 0)
-#define SH_FSI_ACKMD_512 (1 << 0)
-#define SH_FSI_ACKMD_256 (2 << 0)
-#define SH_FSI_ACKMD_128 (3 << 0)
-#define SH_FSI_ACKMD_64 (4 << 0)
-#define SH_FSI_ACKMD_32 (5 << 0)
-
-#define SH_FSI_BPFMD_MASK (0xF << 4)
-#define SH_FSI_BPFMD_512 (1 << 4)
-#define SH_FSI_BPFMD_256 (2 << 4)
-#define SH_FSI_BPFMD_128 (3 << 4)
-#define SH_FSI_BPFMD_64 (4 << 4)
-#define SH_FSI_BPFMD_32 (5 << 4)
-#define SH_FSI_BPFMD_16 (6 << 4)