- val = GRF_EDP_REF_CLK_SEL_INTER | (GRF_EDP_REF_CLK_SEL_INTER << 16);
- writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
-
- val = 0x80008000;
- writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
- dsb(sy);
- val = 0x80008000;
- writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
- dsb(sy);
- udelay(1);
- val = 0x80000000;
- writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
- dsb(sy);
- udelay(1);
+
+ if (cpu_is_rk3288()) {
+ val = GRF_EDP_REF_CLK_SEL_INTER |
+ (GRF_EDP_REF_CLK_SEL_INTER << 16);
+ writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
+
+ val = 0x80008000;
+ writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
+ dsb(sy);
+ udelay(1);
+ val = 0x80000000;
+ writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
+ dsb(sy);
+ udelay(1);
+ } else {
+ val = 0x01 | (0x01 << 16);
+ regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
+
+ reset_control_assert(edp->rst_24m);
+ usleep_range(10, 20);
+ reset_control_deassert(edp->rst_24m);
+ }