org_value = r8712_bb_reg_read(pAdapter, offset);
bit_shift = bitshift(bitmask);
org_value = r8712_bb_reg_read(pAdapter, offset);
bit_shift = bitshift(bitmask);
org_value = r8712_bb_reg_read(pAdapter, offset);
bit_shift = bitshift(bitmask);
new_value = ((org_value & (~bitmask)) | (value << bit_shift));
org_value = r8712_bb_reg_read(pAdapter, offset);
bit_shift = bitshift(bitmask);
new_value = ((org_value & (~bitmask)) | (value << bit_shift));
return r8712_bb_reg_write(pAdapter, offset, new_value);
}
static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
u32 bitmask)
{
return r8712_bb_reg_write(pAdapter, offset, new_value);
}
static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
u32 bitmask)
{
org_value = r8712_rf_reg_read(pAdapter, path, offset);
bit_shift = bitshift(bitmask);
org_value = r8712_rf_reg_read(pAdapter, path, offset);
bit_shift = bitshift(bitmask);
}
static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
}
static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
org_value = r8712_rf_reg_read(pAdapter, path, offset);
bit_shift = bitshift(bitmask);
new_value = ((org_value & (~bitmask)) | (value << bit_shift));
org_value = r8712_rf_reg_read(pAdapter, path, offset);
bit_shift = bitshift(bitmask);
new_value = ((org_value & (~bitmask)) | (value << bit_shift));
return r8712_rf_reg_write(pAdapter, path, offset, new_value);
}
return r8712_rf_reg_write(pAdapter, path, offset, new_value);
}
set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
{
u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
{
u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
- TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
- TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00)>>8;
- TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000)>>16;
- tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
+ TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
+ TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
+ TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
+ tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
* Set Control channel to upper or lower. These settings are
* required only for 40MHz */
set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
* Set Control channel to upper or lower. These settings are
* required only for 40MHz */
set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
HAL_PRIME_CHNL_OFFSET_DONT_CARE);
set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
HAL_PRIME_CHNL_OFFSET_DONT_CARE);
set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
}
set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
}
-void r8712_SetCrystalCap(struct _adapter *pAdapter)
-{
- set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap,
- pAdapter->mppriv.curr_crystalcap);
-}
-