-/**
- * MMU register numbers
- * Used in the register read/write routines.
- * See the hardware documentation for more information about each register
- */
-enum iommu_register {
- /**< Current Page Directory Pointer */
- IOMMU_REGISTER_DTE_ADDR = 0x0000,
- /**< Status of the MMU */
- IOMMU_REGISTER_STATUS = 0x0004,
- /**< Command register, used to control the MMU */
- IOMMU_REGISTER_COMMAND = 0x0008,
- /**< Logical address of the last page fault */
- IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
- /**< Used to invalidate the mapping of a single page from the MMU */
- IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
- /**< Raw interrupt status, all interrupts visible */
- IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
- /**< Indicate to the MMU that the interrupt has been received */
- IOMMU_REGISTER_INT_CLEAR = 0x0018,
- /**< Enable/disable types of interrupts */
- IOMMU_REGISTER_INT_MASK = 0x001C,
- /**< Interrupt status based on the mask */
- IOMMU_REGISTER_INT_STATUS = 0x0020,
- IOMMU_REGISTER_AUTO_GATING = 0x0024
-};
-
-enum iommu_command {
- /**< Enable paging (memory translation) */
- IOMMU_COMMAND_ENABLE_PAGING = 0x00,
- /**< Disable paging (memory translation) */
- IOMMU_COMMAND_DISABLE_PAGING = 0x01,
- /**< Enable stall on page fault */
- IOMMU_COMMAND_ENABLE_STALL = 0x02,
- /**< Disable stall on page fault */
- IOMMU_COMMAND_DISABLE_STALL = 0x03,
- /**< Zap the entire page table cache */
- IOMMU_COMMAND_ZAP_CACHE = 0x04,
- /**< Page fault processed */
- IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
- /**< Reset the MMU back to power-on settings */
- IOMMU_COMMAND_HARD_RESET = 0x06
+struct rk_iommu_domain {
+ struct list_head iommus;
+ struct platform_device *pdev;
+ u32 *dt; /* page directory table */
+ dma_addr_t dt_dma;
+ struct mutex iommus_lock; /* lock for iommus list */
+ struct mutex dt_lock; /* lock for modifying page directory table */
+
+ struct iommu_domain domain;