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ARM: dts: keystone: Fix the mdio bindings by moving it to soc specific file
[firefly-linux-kernel-4.4.55.git]
/
arch
/
mips
/
mti-malta
/
malta-time.c
diff --git
a/arch/mips/mti-malta/malta-time.c
b/arch/mips/mti-malta/malta-time.c
index 185e68261f45937eae2b17dcd502420ce0121f69..5625b190edc061afbf2a8885e976b48014270325 100644
(file)
--- a/
arch/mips/mti-malta/malta-time.c
+++ b/
arch/mips/mti-malta/malta-time.c
@@
-119,18
+119,24
@@
void read_persistent_clock(struct timespec *ts)
int get_c0_fdc_int(void)
{
int get_c0_fdc_int(void)
{
- int mips_cpu_fdc_irq;
+ /*
+ * Some cores claim the FDC is routable through the GIC, but it doesn't
+ * actually seem to be connected for those Malta bitstreams.
+ */
+ switch (current_cpu_type()) {
+ case CPU_INTERAPTIV:
+ case CPU_PROAPTIV:
+ return -1;
+ };
if (cpu_has_veic)
if (cpu_has_veic)
-
mips_cpu_fdc_irq =
-1;
+
return
-1;
else if (gic_present)
else if (gic_present)
-
mips_cpu_fdc_irq =
gic_get_c0_fdc_int();
+
return
gic_get_c0_fdc_int();
else if (cp0_fdc_irq >= 0)
else if (cp0_fdc_irq >= 0)
-
mips_cpu_fdc_irq =
MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
+
return
MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
else
else
- mips_cpu_fdc_irq = -1;
-
- return mips_cpu_fdc_irq;
+ return -1;
}
int get_c0_perfcount_int(void)
}
int get_c0_perfcount_int(void)