+ timer@ff810000 {
+ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xff810000 0x0 0x20>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2s_2ch: i2s-2ch@ff890000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff890000 0x0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
+ status = "disabled";
+ };
+
+ i2s_8ch: i2s-8ch@ff898000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_bus>;
+ status = "disabled";
+ };
+
+ isp: isp@ff910000 {
+ compatible = "rockchip,rk3368-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3368_PD_VIO>;
+ clocks =
+ <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
+ <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
+ <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
+ clock-names =
+ "aclk_isp", "hclk_isp", "clk_isp",
+ "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
+ "clk_cif_pll", "hclk_mipiphy1",
+ "pclk_dphyrx", "clk_vio0_noc";
+
+ pinctrl-names =
+ "default", "isp_dvp8bit2", "isp_dvp10bit",
+ "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
+ "isp_mipi_fl", "isp_mipi_fl_prefl",
+ "isp_flash_as_gpio", "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
+ pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
+ pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
+ pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
+ pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
+ pinctrl-6 = <&cif_clkout>;
+ pinctrl-7 = <&cif_clkout &isp_prelight>;
+ pinctrl-8 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-9 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
+ rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ iommus = <&isp_mmu>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "hclk";
+ rk_iommu,disable_reset_quirk;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3368_PD_VIO>;
+ status = "disabled";
+ };
+
+ vop: vop@ff930000 {
+ compatible = "rockchip,rk3368-vop";
+ reg = <0x0 0xff930000 0x0 0x2fc>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ assigned-clock-rates = <400000000>, <200000000>;
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_mipi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_in_vop>;
+ };
+
+ vop_out_edp: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&edp_in_vop>;
+ };
+ };
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_dsi_host: mipi-dsi-host@ff960000 {
+ compatible = "rockchip,rk3368-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI_DSI0>;
+ clock-names = "pclk";
+ phys = <&mipi_dphy>;
+ phy-names = "mipi_dphy";
+ rockchip,grf = <&grf>;
+ power-domains = <&power RK3368_PD_VIO>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_mipi>;
+ };
+ };
+ };
+ };
+
+ mipi_dphy: mipi-dphy@ff968000 {
+ compatible = "rockchip,rk3368-mipi-dphy";
+ reg = <0x0 0xff968000 0x0 0x4000>;
+ #phy-cells = <0>;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
+ clock-names = "ref", "pclk";
+ status = "disabled";
+ };
+
+ edp: edp@ff970000 {
+ compatible = "rockchip,rk3368-edp";
+ reg = <0x0 0xff970000 0x0 0x8000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ resets = <&cru SRST_EDP>;
+ reset-names = "dp";
+ power-domains = <&power RK3368_PD_VIO>;
+ rockchip,grf = <&grf>;
+ phys = <&edp_phy>;
+ phy-names = "dp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_in: port@0 {
+ reg = <0>;
+
+ edp_in_vop: endpoint {
+ remote-endpoint = <&vop_out_edp>;
+ };
+ };
+ };
+ };
+
+ hevc_mmu: iommu@ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x40>,
+ <0x0 0xff9a0480 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu_mmu", "vdpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu: vpu_service {
+ compatible = "rockchip,vpu_sub";
+ iommu_enabled = <1>;
+ iommus = <&vpu_mmu>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc","irq_dec";
+ dev_mode = <0>;
+ name = "vpu_service";
+ allocator = <1>;
+ };
+
+ hevc: hevc_service {
+ compatible = "rockchip,hevc_sub";
+ iommu_enabled = <1>;
+ iommus = <&hevc_mmu>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ dev_mode = <1>;
+ name = "hevc_service";
+ allocator = <1>;
+ };
+
+ vpu_combo: vpu_combo@ff9a0000 {
+ compatible = "rockchip,vpu_combo";
+ reg = <0x0 0xff9a0000 0x0 0x440>;
+ rockchip,grf = <&grf>;
+ subcnt = <2>;
+ rockchip,sub = <&vpu>, <&hevc>;
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
+ <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec",
+ "clk_core", "clk_cabac";
+ resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
+ <&cru SRST_VIDEO>;
+ reset-names = "video_a", "video_h", "video";
+ mode_bit = <12>;
+ mode_ctrl = <0x418>;
+ name = "vpu_combo";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ status = "disabled";
+ };
+