+
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins =
+ /* mac_rxd3 */
+ <2 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <2 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd2 */
+ <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxd1 */
+ <2 3 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <2 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <2 0 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txclkout */
+ <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_crs */
+ /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
+ /* mac_rxclkin */
+ <2 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <2 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+ <2 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxer */
+ /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
+ /* mac_rxdv */
+ <2 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <2 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* mac_rxd1 */
+ <2 3 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <2 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <2 1 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <2 0 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_crs */
+ /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
+ /* mac_rxclkin */
+ <2 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <2 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <2 12 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <2 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxer */
+ /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
+ /* mac_rxdv */
+ <2 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <2 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ eth_phy {
+ eth_phy_pwr: eth-phy-pwr {
+ rockchip,pins =
+ <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ };
+
+ gpu: gpu@ffa30000 {
+ compatible = "arm,malit764",
+ "arm,malit76x",
+ "arm,malit7xx",
+ "arm,mali-midgard";
+
+ reg = <0x0 0xffa30000 0 0x10000>;
+
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "GPU", "MMU", "JOB";
+
+ clocks = <&cru ACLK_GPU>;
+ clock-names = "clk_mali";
+ operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+ };
+
+ gpu_opp_table: gpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <96000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <192000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <1125000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1200000>;
+ };