# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s # This test ensures that the MIR parser parses virtual register definitions and # references correctly. --- | define i32 @bar(i32 %a) { entry: %0 = icmp sle i32 %a, 10 br i1 %0, label %less, label %exit less: ret i32 0 exit: ret i32 %a } define i32 @foo(i32 %a) { entry: %0 = icmp sle i32 %a, 10 br i1 %0, label %less, label %exit less: ret i32 0 exit: ret i32 %a } ... --- name: bar isSSA: true tracksRegLiveness: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gr32 } # CHECK-NEXT: - { id: 1, class: gr32 } # CHECK-NEXT: - { id: 2, class: gr32 } registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } - { id: 2, class: gr32 } body: | bb.0.entry: successors: %bb.2.exit, %bb.1.less liveins: %edi ; CHECK: %0 = COPY %edi ; CHECK-NEXT: %1 = SUB32ri8 %0, 10 %0 = COPY %edi %1 = SUB32ri8 %0, 10, implicit-def %eflags JG_1 %bb.2.exit, implicit %eflags JMP_1 %bb.1.less bb.1.less: ; CHECK: %2 = MOV32r0 ; CHECK-NEXT: %eax = COPY %2 %2 = MOV32r0 implicit-def %eflags %eax = COPY %2 RETQ %eax bb.2.exit: %eax = COPY %0 RETQ %eax ... --- name: foo isSSA: true tracksRegLiveness: true # CHECK: name: foo # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gr32 } # CHECK-NEXT: - { id: 1, class: gr32 } # CHECK-NEXT: - { id: 2, class: gr32 } registers: - { id: 2, class: gr32 } - { id: 0, class: gr32 } - { id: 10, class: gr32 } body: | bb.0.entry: successors: %bb.2.exit, %bb.1.less liveins: %edi ; CHECK: %0 = COPY %edi ; CHECK-NEXT: %1 = SUB32ri8 %0, 10 %2 = COPY %edi %0 = SUB32ri8 %2, 10, implicit-def %eflags JG_1 %bb.2.exit, implicit %eflags JMP_1 %bb.1.less bb.1.less: ; CHECK: %2 = MOV32r0 ; CHECK-NEXT: %eax = COPY %2 %10 = MOV32r0 implicit-def %eflags %eax = COPY %10 RETQ %eax bb.2.exit: ; CHECK: %eax = COPY %0 %eax = COPY %2 RETQ %eax ...