#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
#include "rk3288-pinctrl.dtsi"
#include <dt-bindings/rkfb/rk_fb.h>

/ {
	compatible = "rockchip,rk3288";
	interrupt-parent = <&gic>;

	aliases {
		serial2 = &uart_dbg;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		lcdc0 = &lcdc0;
		lcdc1 = &lcdc1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x500>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x501>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x502>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x503>;
		};
	};

	gic: interrupt-controller@ffc01000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;
		reg = <0xffc01000 0x1000>,
		      <0xffc02000 0x1000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	timer@ff810000 {
		compatible = "rockchip,timer";
		reg = <0xff810000 0x20>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,broadcast = <1>;
	};

	timer@ff810020 {
		compatible = "rockchip,timer";
		reg = <0xff810020 0x20>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,clocksource = <1>;
		rockchip,count-up = <1>;
	};

	uart_dbg: serial@ff690000 {
		compatible = "rockchip,serial";
		reg = <0xff690000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <106>;
		rockchip,wake-irq = <0>;
		status = "disabled";
	};

	i2c0: i2c@ff650000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff650000 0x1000>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c0_sda &i2c0_scl>;
		//pinctrl-1 = <&i2c0_gpio>;
		//gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 4>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c1: i2c@ff140000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff140000 0x1000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c1_sda &i2c1_scl>;
		//pinctrl-1 = <&i2c1_gpio>;
		//gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 5>;
        rockchip,check-idle = <1>;
        status = "disabled";
	};

	i2c2: i2c@ff660000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff660000 0x1000>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c2_sda &i2c2_scl>;
		//pinctrl-1 = <&i2c2_gpio>;
		//gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 6>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c3: i2c@ff150000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff150000 0x1000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c3_sda &i2c3_scl>;
		//pinctrl-1 = <&i2c3_gpio>;
		//gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 7>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c4: i2c@ff160000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff160000 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c4_sda &i2c4_scl>;
		//pinctrl-1 = <&i2c4_gpio>;
		//gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 8>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};
	
	i2c5: i2c@ff170000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff170000 0x1000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c5_sda &i2c5_scl>;
		//pinctrl-1 = <&i2c5_gpio>;
		//gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 8>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	edp: edp@ff970000 {
		compatible = "rockchip,rk32-edp";
		reg = <0xff970000 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
        };

	hdmi: hdmi@ff980000 {
		compatible = "rockchip,rk3288-hdmi";
		reg = <0xff980000 0x20000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,hdmi_lcdc_source = <1>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c5_sda &i2c5_scl>;
		pinctrl-1 = <&i2c5_gpio>;
		status = "disabled";
	};
	fb: fb{
		compatible = "rockchip,rk-fb";
		rockchip,disp-mode = <DUAL>;
	};

	lcdc0: lcdc@ff940000 {
		compatible = "rockchip,rk3288-lcdc";
		rockchip,prop = <PRMRY>;
		rochchip,pwr18 = <0>;
		reg = <0xff940000 0x10000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&lcdc0_lcdc>;
		//pinctrl-1 = <&lcdc0_gpio>;		
		status = "disabled";
	};

	lcdc1: lcdc@ff930000 {
		compatible = "rockchip,rk3288-lcdc";
		rockchip,prop = <EXTEND>;
		rockchip,pwr18 = <0>;
		reg = <0xff930000 0x10000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&lcdc0_lcdc>;
		pinctrl-1 = <&lcdc0_gpio>;
		status = "disabled";
	};

	adc: adc@ff100000 {
		compatible = "rockchip,saradc";
		reg = <0xff100000 0x100>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		io-channel-ranges;
		rockchip,adc-vref = <1800>;
		clock-frequency = <1000000>;
		clock-names = "saradc", "pclk_saradc";
		status = "disabled";
	};

	rga@ff920000 {
		compatible = "rockchip,rga";
		reg = <0xff920000 0x1000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "hclk_rga", "aclk_rga"; 
	};

	i2s: rockchip-i2s@0xff890000 {
		compatible = "rockchip-i2s";
		reg = <0xff890000 0x10000>;
		i2s-id = <0>;
	//	clocks = <&clk_i2s>;
	//	clock-names = "i2s_clk","i2s_mclk";
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	//	dmas = <&pdma0 0>,
	//		<&pdma0 1>;
		//#dma-cells = <2>;
	//	dma-names = "tx", "rx";
	//	pinctrl-names = "default", "sleep";
	//	pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
	//	pinctrl-1 = <&i2s0_gpio>;
	};

	spdif: rockchip-spdif@0xff8b0000 {
		compatible = "rockchip-spdif";
		reg = <0xff8b0000 0x10000>;	//8channel
		//reg = <ff880000 0x2000>;//2channel
	//	clocks = <&clk_spdif>;
	//	clock-names = "spdif_mclk";
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	//	dmas = <&pdma0 8>;
		//#dma-cells = <1>;
	//	dma-names = "tx";
	//	pinctrl-names = "default";
	//	pinctrl-0 = <&spdif_tx>;
	};

	ion: ion {
		compatible = "rockchip,ion";
		#address-cells = <1>;
		#size-cells = <0>;
		rockchip,ion-heap@1 { /* CMA HEAP */
			reg = <1>;
		};
		rockchip,ion-heap@3 { /* SYSTEM HEAP */
			reg = <3>;
		};
	};

	mmc: mshc@ff0c0000 {
		compatible = "rockchip,rk_mmc";
		reg = <0xff0c0000 0x4000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default","suspend";
		//pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
		//pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
		//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
		//clock-names = "hclk_mmc","mmc";
		clock-frequency = <50000000>;
		clock-freq-min-max = <400000 50000000>;
		num-slots = <1>;
		supports-highspeed;
		broken-cd;
		card-detect-delay = <200>;
		pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
		fifo-depth = <0x100>;
		emmc-compatible = <0>;
		status = "okay";
	};

	sdio0: mshc@ff0d0000 {
		compatible = "rockchip,rk_mmc";
		reg = <0xff0d0000 0x4000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
		//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
		//clock-names = "hclk_sdio0","sdio0";
		clock-frequency = <50000000>;
		clock-freq-min-max = <400000 50000000>;
		num-slots = <1>;
		supports-highspeed;
		fifo-depth = <0x100>;
		emmc-compatible = <0>;
		status = "disabled";
	};
	
	sdio1: mshc@ff0e0000 {
		compatible = "rockchip,rk_mmc";
		reg = <0xff0e0000 0x4000>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
		//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
		//clock-names = "hclk_sdio1","sdio1";
		clock-frequency = <50000000>;
		clock-freq-min-max = <400000 50000000>;
		num-slots = <1>;
		supports-highspeed;
		fifo-depth = <0x100>;
		emmc-compatible = <0>;
		status = "disabled";
	};
	
	emmc: mshc@ff0f0000 {
		compatible = "rockchip,rk_mmc";
		reg = <0xff0f0000 0x4000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
		//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
		//clock-names = "hclk_sdio1","sdio1";
		clock-frequency = <50000000>;
		clock-freq-min-max = <400000 50000000>;
		num-slots = <1>;
		supports-highspeed;
		fifo-depth = <0x100>;
		emmc-compatible = <1>;
		status = "disabled";
	};
	
	vpu: vpu_service@ff9a0000 {
		compatible = "vpu_service";
		reg = <0xff9a0000 0x800>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc", "irq_dec";
		/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
		clock-names = "aclk_vcodec", "hclk_vcodec"; */
		name = "vpu_service";
		status = "disabled";
	};

	hevc: hevc_service@ff9c0000 {
		compatible = "rockchip,hevc_service";
		reg = <0xff9c0000 0x800>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
		clock-names = "aclk_vcodec", "hclk_vcodec";*/
		name = "hevc_service";
		status = "disabled";
	};

	iep: iep@ff900000 {
		compatible = "rockchip,iep";
		reg = <0xff900000 0x800>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		/*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
		clock_names = "aclk_iep", "hclk_iep";*/
		status = "disabled";
        };
};