#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
#include "rk3288-pinctrl.dtsi"

/ {
	compatible = "rockchip,rk3288";
	interrupt-parent = <&gic>;

	aliases {
		serial2 = &uart_dbg;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x500>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x501>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x502>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x503>;
		};
	};

	gic: interrupt-controller@ffc01000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;
		reg = <0xffc01000 0x1000>,
		      <0xffc02000 0x1000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	timer@ff810000 {
		compatible = "rockchip,timer";
		reg = <0xff810000 0x20>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,broadcast = <1>;
	};

	timer@ff810020 {
		compatible = "rockchip,timer";
		reg = <0xff810020 0x20>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,clocksource = <1>;
		rockchip,count-up = <1>;
	};

	uart_dbg: serial@ff690000 {
		compatible = "rockchip,serial";
		reg = <0xff690000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <106>;
		rockchip,wake-irq = <0>;
		status = "disabled";
	};



	i2c0: i2c@ff650000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff650000 0x1000>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c0_sda &i2c0_scl>;
		//pinctrl-1 = <&i2c0_gpio>;
		//gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 4>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c1: i2c@ff140000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff140000 0x1000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c1_sda &i2c1_scl>;
		//pinctrl-1 = <&i2c1_gpio>;
		//gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 5>;
	   rockchip,check-idle = <1>;	
      status = "disabled";


	};

	i2c2: i2c@ff660000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff660000 0x1000>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c2_sda &i2c2_scl>;
		//pinctrl-1 = <&i2c2_gpio>;
		//gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 6>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c3: i2c@ff150000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff150000 0x1000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c2_sda &i2c2_scl>;
		//pinctrl-1 = <&i2c2_gpio>;
		//gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 6>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c4: i2c@ff160000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff160000 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c3_sda &i2c3_scl>;
		//pinctrl-1 = <&i2c3_gpio>;
		//gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 7>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

   i2c5: i2c@ff170000 {
       compatible = "rockchip,rk30-i2c";
       reg = <0xff170000 0x1000>;
       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
       #address-cells = <1>;
       #size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c4_sda &i2c4_scl>;
		//pinctrl-1 = <&i2c4_gpio>;
		//gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
		//clocks = <&clk_gates8 8>;
       rockchip,check-idle = <1>;
       status = "disabled";
    };

    adc: adc@ff100000 {
        compatible = "rockchip,saradc";
        reg = <0xff100000 0x100>;
        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
        #io-channel-cells = <1>;
        io-channel-ranges;
        rockchip,adc-vref = <1800>;
        clock-frequency = <1000000>;
        clock-names = "saradc", "pclk_saradc"; 
        status = "disabled";
    };
	
	rga@ff930000 {
		compatible = "rockchip,rga";
		reg = <0xff930000 0x1000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
    clock-names = "hclk_rga", "aclk_rga"; 
		status = "disabled";
        };

	i2s: rockchip-i2s@0xff890000 {
		compatible = "rockchip-i2s";
		reg = <0xff890000 0x10000>;
		i2s-id = <0>;
	//	clocks = <&clk_i2s>;
	//	clock-names = "i2s_clk","i2s_mclk";
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	//	dmas = <&pdma0 0>,
	//		<&pdma0 1>;
		//#dma-cells = <2>;
	//	dma-names = "tx", "rx";
	//	pinctrl-names = "default", "sleep";
	//	pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
	//	pinctrl-1 = <&i2s0_gpio>;
	};

	spdif: rockchip-spdif@0xff8b0000 {
		compatible = "rockchip-spdif";
		reg = <0xff8b0000 0x10000>;	//8channel
		//reg = <ff880000 0x2000>;//2channel
	//	clocks = <&clk_spdif>;
	//	clock-names = "spdif_mclk";
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	//	dmas = <&pdma0 8>;
		//#dma-cells = <1>;
	//	dma-names = "tx";
	//	pinctrl-names = "default";
	//	pinctrl-0 = <&spdif_tx>;
	};
	ion: ion{
		compatible = "rockchip,ion";
		#address-cells = <1>;
		#size-cells = <0>;
		rockchip,ion-heap@1 { /* CMA HEAP */
			reg = <1>;
		};
		rockchip,ion-heap@3 { /* SYSTEM HEAP */
			reg = <3>;
		};
	};
};