#include "skeleton.dtsi"
#include "rk3188-pinctrl.dtsi"
#include <dt-bindings/rkfb/rk_fb.h>


/ {
	compatible = "rockchip,rk3188";
	interrupt-parent = <&gic>;
	rockchip,sram = <&sram>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		lcdc0 = &lcdc0;
		lcdc1 = &lcdc1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	twd-wdt@1013c620 {
		compatible = "arm,cortex-a9-twd-wdt";
		reg = <0x1013c620 0x20>;
		interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gic: interrupt-controller@1013d000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x1013d000 0x1000>,
		      <0x1013c100 0x0100>;
	};

	L2: cache-controller@10138000 {
		compatible = "rockchip,pl310-cache", "arm,pl310-cache";
		reg = <0x10138000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <1 1 1>;
		arm,data-latency = <3 1 2>;
		rockchip,prefetch-ctrl = <0x70000003>;
		/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
		rockchip,power-ctrl = <0x3>;
/*
		(0x1 << 0) |	// Full line of write zero behavior Enabled
		(0x1 << 25) | 	// Round-robin replacement
		(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
*/
		rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
	};

	cpu_axi_bus: cpu_axi_bus@10128000 {
		compatible = "rockchip,cpu_axi_bus";
		reg = <0x10128000 0x8000>;
		qos {
			dmac {
				rockchip,offset = <0x1000>;
				rockchip,priority = <0 0>;
			};
			cpu0 {
				rockchip,offset = <0x2000>;
				rockchip,priority = <0 0>;
			};
			cpu1r {
				rockchip,offset = <0x2080>;
				rockchip,priority = <0 0>;
			};
			cpu1w {
				rockchip,offset = <0x2100>;
				rockchip,priority = <0 0>;
			};
			peri {
				rockchip,offset = <0x4000>;
				rockchip,priority = <2 2>;
			};
			gpu {
				rockchip,offset = <0x5000>;
				rockchip,priority = <2 1>;
			};
			vpu {
				rockchip,offset = <0x6000>;
			};
			vop0 {
				rockchip,offset = <0x7000>;
				rockchip,priority = <3 3>;
			};
			cif0 {
				rockchip,offset = <0x7080>;
			};
			ipp {
				rockchip,offset = <0x7100>;
			};
			vop1 {
				rockchip,offset = <0x7180>;
				rockchip,priority = <3 3>;
			};
			cif1 {
				rockchip,offset = <0x7200>;
			};
			rga {
				rockchip,offset = <0x7280>;
			};
		};
	};

	bootrom@10120000 {
		compatible = "rockchip,bootrom";
		reg = <0x10120000 0x4000>;
	};

	bootram@10080000 {
		compatible = "rockchip,bootram";
		reg = <0x10080000 0x20>; /* 32 bytes */
	};

	sram: sram@10080020 {
		compatible = "mmio-sram";
		reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
		map-exec;
	};

	pmu@20004000 {
		compatible = "rockchip,pmu";
		reg = <0x20004000 0x4000>;
	};

	timer@20038000 {
		compatible = "rockchip,timer";
		reg = <0x20038000 0x20>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,percpu = <0>;
	};

	timer@20038020 {
		compatible = "rockchip,timer";
		reg = <0x20038020 0x20>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,percpu = <1>;
	};

	timer@20038040 {
		compatible = "rockchip,timer";
		reg = <0x20038040 0x20>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,percpu = <2>;
	};

	timer@20038060 {
		compatible = "rockchip,timer";
		reg = <0x20038060 0x20>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,percpu = <3>;
	};

	timer@20038080 {
		compatible = "rockchip,timer";
		reg = <0x20038080 0x20>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,broadcast = <1>;
	};

	timer@200380a0 {
		compatible = "rockchip,timer";
		reg = <0x200380a0 0x20>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,clocksource = <1>;
	};

	uart0: serial@10124000 {
		compatible = "rockchip,serial";
		reg = <0x10124000 0x100>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	uart1: serial@10126000 {
		compatible = "rockchip,serial";
		reg = <0x10126000 0x100>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
		status = "disabled";
	};

	uart2: serial@20064000 {
		compatible = "rockchip,serial";
		reg = <0x20064000 0x100>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		current-speed = <115200>;
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	uart3: serial@20068000 {
		compatible = "rockchip,serial";
		reg = <0x20068000 0x100>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <112>;
		rockchip,wake-irq = <0>;
		status = "disabled";
	};

	i2c0: i2c@2002d000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x2002d000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c0_sda &i2c0_scl>;
		pinctrl-1 = <&i2c0_gpio>;
		gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 4>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c1: i2c@2002f000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x2002f000 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c1_sda &i2c1_scl>;
		pinctrl-1 = <&i2c1_gpio>;
		gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 5>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c2: i2c@20055000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x20055000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c2_sda &i2c2_scl>;
		pinctrl-1 = <&i2c2_gpio>;
		gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 6>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c3: i2c@20059000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x20059000 0x1000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c3_sda &i2c3_scl>;
		pinctrl-1 = <&i2c3_gpio>;
		gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 7>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c4: i2c@2005d000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x2005d000 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&i2c4_sda &i2c4_scl>;
		pinctrl-1 = <&i2c4_gpio>;
		gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 8>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	clocks-init{
		compatible = "rockchip,clocks-init";
		rockchip,clocks-init-parent =
			<&clk_core &clk_apll>,	<&aclk_cpu_mux &clk_gpll>,/*FIXME*/
			<&aclk_peri_mux &clk_gpll>,	<&clk_i2s_pll_mux &clk_cpll>,
			<&clk_uart_pll_mux &clk_gpll>;
		rockchip,clocks-init-rate =
			<&clk_core 594000000>,	<&clk_gpll 768000000>,
			<&clk_cpll 594000000>,	<&aclk_cpu 192000000>,
			<&hclk_cpu 96000000>,	<&pclk_cpu 48000000>,
			<&pclk_ahb2apb 48000000>,	<&aclk_peri 192000000>,
			<&hclk_peri 96000000>,	<&pclk_peri 48000000>,
			<&clk_gpu 200000000>;
	};

	fb: fb{
		compatible = "rockchip,rk-fb";
		rockchip,disp-mode = <DUAL>;
	};

	nandc: nandc {
		compatible = "rockchip,rk-nandc";
		reg = <0x10050000 0x4000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	};

	lcdc0:lcdc@1010c000 {
		compatible = "rockchip,rk3188-lcdc";
		rockchip,prop = <PRMRY>;
		rochchip,pwr18 = <0>;
		reg = <0x1010c000 0x1000>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	lcdc1:lcdc@1010e000 {
		compatible = "rockchip,rk3188-lcdc";
		rockchip,prop = <EXTEND>;
		rockchip,pwr18 = <0>;
		reg = <0x1010e000 0x1000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&lcdc1_lcdc>;
		pinctrl-1 = <&lcdc1_gpio>;
		status = "disabled";
        };

	pwm0: pwm@20030000{
                compatible = "rockchip,pwm";
                reg = <0x20030000 0x10>; 
                #pwm-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm0_pin>;
                status = "disabled";

        };

        pwm1: pwm@20030010{
                compatible = "rockchip,pwm";
                reg = <0x20030010 0x10>; /*0x20030000*/
                #pwm-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm1_pin>;
                status = "disabled";

        };
    	pwm2: pwm@20050020{
                compatible = "rockchip,pwm";
                reg = <0x20050020 0x10>; /*0x20030000*/
                #pwm-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm2_pin>;
                status = "disabled";

        };

        pwm3: pwm@20050030{
                compatible = "rockchip,pwm";
                reg = <0x20050030 0x10>; /*0x20030000*/
                #pwm-cells = <2>;
                pinctrl-names = "default";
                pinctrl-0 = <&pwm3_pin>;
                status = "disabled";

        };
	dvfs {
		vd_cpu:
		vd_cpu {
			regulator_name="vdd_arm";
			suspend_volt=<1000>; //mV
			pd_a9 {
				clk_core_dvfs_table:
				clk_core {
					operating-points = <
						/* KHz    uV */
						312000 900000
						504000 950000
						816000 1000000
						1008000 1100000
						1200000 1200000
						1416000 1300000
						1608000 1350000
						>;
				};
			};
		};

		vd_core:
		vd_core {
			regulator_name="vdd_logic";
			suspend_volt=<1000>; //mV

			pd_gpu {
				clk_gpu_dvfs_table:
				clk_gpu {
					operating-points = <
						/* KHz    uV */
						200000 1200000
						300000 1200000
						400000 1200000
						>;
				};
			};

			pd_ddr {
				clk_ddr_dvfs_table:
				clk_ddr {
					operating-points = <
						/* KHz    uV */
						200000 1200000
						300000 1200000
						400000 1200000
						>;
				};
			};
		};
	};
};