#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"
#include "rk3036-clocks.dtsi"

/ {
	compatible = "rockchip,rk3036";
	rockchip,sram = <&sram>;
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		spi0 = &spi0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
		};
	};

	gic: interrupt-controller@10139000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;
		reg = <0x10139000 0x1000>,
		      <0x1013a000 0x1000>;
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x2000>;
		map-exec;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	watchdog: wdt@2004c000 {
		compatible = "rockchip,watch dog";
		reg = <0x2004c000 0x100>;
		clocks = <&clk_gates7 15>;
		clock-names = "pclk_wdt";
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,irq = <1>;
		rockchip,timeout = <60>;
		rockchip,atboot = <1>;
		rockchip,debug = <0>;
		status = "disabled";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;

		pdma: pdma@20078000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20078000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
		};
	};

	nandc: nandc@10500000 {
		compatible = "rockchip,rk-nandc";
		reg = <0x10500000 0x4000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
                nandc_id = <0>;
		clocks = <&clk_nandc>, <&clk_gates5 9>;
		clock-names = "clk_nandc", "hclk_nandc";
	};

	spi0: spi@20074000 {
		compatible = "rockchip,rockchip-spi";
		reg = <0x20074000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
		rockchip,spi-src-clk = <0>;
		num-cs = <2>;
		//clocks =<&clk_spi0>, <&clk_gates7 12>;
		//clock-names = "spi","pclk_spi0";
		//dmas = <&pdma 8>, <&pdma 9>;
		//#dma-cells = <2>;
		//dma-names = "tx", "rx";
		status = "disabled";
	};

	uart0: serial@20060000 {
		compatible = "rockchip,serial";
		reg = <0x20060000 0x100>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&clk_uart0>, <&clk_gates8 0>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&pdma 2>, <&pdma 3>;
		#dma-cells = <2>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	uart1: serial@20064000 {
		compatible = "rockchip,serial";
		reg = <0x20064000 0x100>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&clk_uart1>, <&clk_gates8 1>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&pdma 4>, <&pdma 5>;
		#dma-cells = <2>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
		status = "disabled";
	};

	uart2: serial@20068000 {
		compatible = "rockchip,serial";
		reg = <0x20068000 0x100>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&clk_uart2>, <&clk_gates8 2>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&pdma 6>, <&pdma 7>;
		#dma-cells = <2>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <106>;
		rockchip,wake-irq = <0>;
		status = "disabled";
	};

	i2c0: i2c@20072000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x20072000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c0_sda &i2c0_scl>;
		//pinctrl-1 = <&i2c0_gpio>;
		//gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 4>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c1: i2c@20056000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c1_sda &i2c1_scl>;
		//pinctrl-1 = <&i2c1_gpio>;
		//gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 5>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2c2: i2c@2005a000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "gpio";
		//pinctrl-0 = <&i2c2_sda &i2c2_scl>;
		//pinctrl-1 = <&i2c2_gpio>;
		//gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates8 6>;
		rockchip,check-idle = <1>;
		status = "disabled";
	};

	i2s: i2s@10220000 {
		compatible = "rockchip-i2s";
		reg = <0x10220000 0x1000>;
		i2s-id = <0>;
		clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
		clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&pdma 0>, <&pdma 1>;
		//#dma-cells = <2>;
		dma-names = "tx", "rx";
		//pinctrl-names = "default", "sleep";
		//pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
		//pinctrl-1 = <&i2s_gpio>;
	};

	spdif: spdif@10204000 {
		compatible = "rockchip-spdif";
		reg = <0x10204000 0x1000>;
		clocks = <&clk_spdif>;
		clock-names = "spdif_mclk";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&pdma 13>;
		//#dma-cells = <1>;
		dma-names = "tx";
		//pinctrl-names = "default";
		//pinctrl-0 = <&spdif_tx>;
	};

	pwm0: pwm@20050000 {
		compatible = "rockchip,rk-pwm";
		reg = <0x20050000 0x10>;
		#pwm-cells = <2>;
		//pinctrl-names = "default";
		//pinctrl-0 = <&pwm_pin>;
		clocks = <&clk_gates7 10>;
		clock-names = "pclk_pwm";
		status = "disabled";
	};

        pwm1: pwm@20050010 {
                compatible = "rockchip,rk-pwm";
                reg = <0x20050010 0x10>;
                #pwm-cells = <2>;
                //pinctrl-names = "default";
                //pinctrl-0 = <&pwm_pin>;
                clocks = <&clk_gates7 10>;
                clock-names = "pclk_pwm";
                status = "disabled";
        };

        pwm2: pwm@20050020 {
                compatible = "rockchip,rk-pwm";
                reg = <0x20050020 0x10>;
                #pwm-cells = <2>;
                //pinctrl-names = "default";
                //pinctrl-0 = <&pwm_pin>;
                clocks = <&clk_gates7 10>;
                clock-names = "pclk_pwm";
                status = "disabled";
        };

        pwm3: pwm@20050030 {
                compatible = "rockchip,rk-pwm";
                reg = <0x20050030 0x10>;
                #pwm-cells = <2>;
                //pinctrl-names = "default";
                //pinctrl-0 = <&pwm_pin>;
                clocks = <&clk_gates7 10>;
                clock-names = "pclk_pwm";
                status = "disabled";
        };

	emmc: rksdmmc@1021c000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
		reg = <0x1021c000 0x4000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default",,"suspend";
		//pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
		clocks = <&clk_emmc>, <&clk_gates7 0>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <1>;
		fifo-depth = <0x100>;
		bus-width = <8>;
	};


	sdmmc: rksdmmc@10214000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
		reg = <0x10214000 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default", "idle";
		//pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
		//pinctrl-1 = <&sdmmc0_gpio>;
		//cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
		clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <1>;
		fifo-depth = <0x100>;
		bus-width = <4>;
	};

	sdio: rksdmmc@10218000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
		reg = <0x10218000 0x4000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		//pinctrl-names = "default","idle";
		//pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
		//pinctrl-1 = <&sdio_gpio>;
		clocks = <&clk_sdio>, <&clk_gates5 11>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <1>;
		fifo-depth = <0x100>;
		bus-width = <4>;
	};
	gpu {
		compatible = "arm,mali400";
		reg = <0x10091000 0x200>,
			  <0x10090000 0x100>,
			  <0x10093000 0x100>,
			  <0x10098000 0x1100>,
			  <0x10094000 0x100>;
		reg-names = "Mali_L2",
					"Mali_GP",
					"Mali_GP_MMU",
					"Mali_PP0",
					"Mali_PP0_MMU";

	    interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			  	     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	    interrupt-names = "Mali_GP_IRQ", 
						  "Mali_GP_MMU_IRQ", 
						  "Mali_PP0_IRQ",
						  "Mali_PP0_MMU_IRQ";
	  };
	dwc_control_usb: dwc-control-usb@20008000 {
		compatible = "rockchip,rk3188-dwc-control-usb";
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "otg_bvalid";
		//gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
		clocks = <&clk_gates9 13>;
		clock-names = "hclk_usb_peri";
		rockchip,remote_wakeup;
		rockchip,usb_irq_wakeup;

		usb_bc{
			compatible = "rockchip,ctrl";
			rk_usb,bvalid   = <0x14c 8 1>;
			rk_usb,iddig	= <0x14c 11 1>;
			rk_usb,line	= <0x14c 9 2>;
			rk_usb,softctrl = <0x17c 0 1>;
			rk_usb,opmode   = <0x17c 2 2>;
			rk_usb,xcvrsel  = <0x17c 4 2>;
			rk_usb,termsel  = <0x118 6 1>; 
		};
	};
	usb0: usb@10180000 {
		compatible = "rockchip,rk3188_usb20_otg";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates1 5>, <&clk_gates5 13>;
		clock-names = "clk_usbphy0", "hclk_usb0";
		/*0 - Normal, 1 - Force Host, 2 - Force Device*/
		rockchip,usb-mode = <0>;
	};

	usb1: usb@101c0000 {
		compatible = "rockchip,rk3188_usb20_host";
		reg = <0x101c0000 0x40000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_gates1 6>, <&clk_gates7 3>;
		clock-names = "clk_usbphy1", "hclk_usb1";
	};

        vpu: vpu_service@10108000 {
		compatible = "vpu_service";
		reg = <0x10108000 0x800>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc", "irq_dec";
		clocks = <&clk_vdpu>, <&hclk_vdpu>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		name = "vpu_service";
		status = "disabled";
	};

	hevc: hevc_service@1010c000 {
		compatible = "rockchip,hevc_service";
		reg = <0x1010c000 0x800>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
		name = "hevc_service";
		status = "disabled";
	};
};