1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
39 // A clone of X86 since we can't depend on something that is generated.
49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55 #define MAP(from, to) MRM_##from = to,
64 D8 = 3, D9 = 4, DA = 5, DB = 6,
65 DC = 7, DD = 8, DE = 9, DF = 10,
68 P_0F_AE = 16, P_0F_01 = 17
72 // If rows are added to the opcode extension tables, then corresponding entries
73 // must be added here.
75 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
76 // that byte to ONE_BYTE_EXTENSION_TABLES.
78 // If the row corresponds to two bytes where the first is 0f, add an entry for
79 // the second byte to TWO_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to some other set of bytes, you will need to modify
82 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83 // to the X86 TD files, except in two cases: if the first two bytes of such a
84 // new combination are 0f 38 or 0f 3a, you just have to add maps called
85 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87 // in RecognizableInstr::emitDecodePath().
89 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d1) \
101 EXTENSION_TABLE(d2) \
102 EXTENSION_TABLE(d3) \
103 EXTENSION_TABLE(f6) \
104 EXTENSION_TABLE(f7) \
105 EXTENSION_TABLE(fe) \
108 #define TWO_BYTE_EXTENSION_TABLES \
109 EXTENSION_TABLE(00) \
110 EXTENSION_TABLE(01) \
111 EXTENSION_TABLE(18) \
112 EXTENSION_TABLE(71) \
113 EXTENSION_TABLE(72) \
114 EXTENSION_TABLE(73) \
115 EXTENSION_TABLE(ae) \
116 EXTENSION_TABLE(b9) \
117 EXTENSION_TABLE(ba) \
120 using namespace X86Disassembler;
122 /// needsModRMForDecode - Indicates whether a particular instruction requires a
123 /// ModR/M byte for the instruction to be properly decoded. For example, a
124 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that a ModR/M byte is required, false
130 static bool needsModRMForDecode(uint8_t form) {
131 if (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMDestMem ||
133 form == X86Local::MRMSrcReg ||
134 form == X86Local::MRMSrcMem ||
135 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142 /// isRegFormat - Indicates whether a particular form requires the Mod field of
143 /// the ModR/M byte to be 0b11.
145 /// @param form - The form of the instruction.
146 /// @return - true if the form implies that Mod must be 0b11, false
148 static bool isRegFormat(uint8_t form) {
149 if (form == X86Local::MRMDestReg ||
150 form == X86Local::MRMSrcReg ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158 /// Useful for switch statements and the like.
160 /// @param init - A reference to the BitsInit to be decoded.
161 /// @return - The field, with the first bit in the BitsInit as the lowest
163 static uint8_t byteFromBitsInit(BitsInit &init) {
164 int width = init.getNumBits();
166 assert(width <= 8 && "Field is too large for uint8_t!");
173 for (index = 0; index < width; index++) {
174 if (static_cast<BitInit*>(init.getBit(index))->getValue())
183 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184 /// name of the field.
186 /// @param rec - The record from which to extract the value.
187 /// @param name - The name of the field in the record.
188 /// @return - The field, as translated by byteFromBitsInit().
189 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190 BitsInit* bits = rec->getValueAsBitsInit(name);
191 return byteFromBitsInit(*bits);
194 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195 const CodeGenInstruction &insn,
200 Name = Rec->getName();
201 Spec = &tables.specForUID(UID);
203 if (!Rec->isSubClassOf("X86Inst")) {
204 ShouldBeEmitted = false;
208 Prefix = byteFromRec(Rec, "Prefix");
209 Opcode = byteFromRec(Rec, "Opcode");
210 Form = byteFromRec(Rec, "FormBits");
211 SegOvr = byteFromRec(Rec, "SegOvrBits");
213 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
214 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
215 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
216 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
217 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
219 Name = Rec->getName();
220 AsmString = Rec->getValueAsString("AsmString");
222 Operands = &insn.OperandList;
224 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
225 HasFROperands = false;
227 ShouldBeEmitted = true;
230 void RecognizableInstr::processInstr(DisassemblerTables &tables,
231 const CodeGenInstruction &insn,
234 // Ignore "asm parser only" instructions.
235 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
238 RecognizableInstr recogInstr(tables, insn, uid);
240 recogInstr.emitInstructionSpecifier(tables);
242 if (recogInstr.shouldBeEmitted())
243 recogInstr.emitDecodePath(tables);
246 InstructionContext RecognizableInstr::insnContext() const {
247 InstructionContext insnContext;
249 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
250 if (HasREX_WPrefix && HasOpSizePrefix)
251 insnContext = IC_64BIT_REXW_OPSIZE;
252 else if (HasOpSizePrefix)
253 insnContext = IC_64BIT_OPSIZE;
254 else if (HasREX_WPrefix && Prefix == X86Local::XS)
255 insnContext = IC_64BIT_REXW_XS;
256 else if (HasREX_WPrefix && Prefix == X86Local::XD)
257 insnContext = IC_64BIT_REXW_XD;
258 else if (Prefix == X86Local::XD)
259 insnContext = IC_64BIT_XD;
260 else if (Prefix == X86Local::XS)
261 insnContext = IC_64BIT_XS;
262 else if (HasREX_WPrefix)
263 insnContext = IC_64BIT_REXW;
265 insnContext = IC_64BIT;
268 insnContext = IC_OPSIZE;
269 else if (Prefix == X86Local::XD)
271 else if (Prefix == X86Local::XS)
280 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
281 // Filter out intrinsics
283 if (!Rec->isSubClassOf("X86Inst"))
284 return FILTER_STRONG;
286 if (Form == X86Local::Pseudo ||
288 return FILTER_STRONG;
290 if (Form == X86Local::MRMInitReg)
291 return FILTER_STRONG;
294 // Filter out instructions with a LOCK prefix;
295 // prefer forms that do not have the prefix
299 // Filter out artificial instructions
301 if (Name.find("TAILJMP") != Name.npos ||
302 Name.find("_Int") != Name.npos ||
303 Name.find("_int") != Name.npos ||
304 Name.find("Int_") != Name.npos ||
305 Name.find("_NOREX") != Name.npos ||
306 Name.find("_TC") != Name.npos ||
307 Name.find("EH_RETURN") != Name.npos ||
308 Name.find("V_SET") != Name.npos ||
309 Name.find("LOCK_") != Name.npos ||
310 Name.find("WIN") != Name.npos)
311 return FILTER_STRONG;
315 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
317 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
320 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
322 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
324 if (Name.find("Fs") != Name.npos)
326 if (Name == "MOVLPDrr" ||
327 Name == "MOVLPSrr" ||
333 Name == "MOVSX16rm8" ||
334 Name == "MOVSX16rr8" ||
335 Name == "MOVZX16rm8" ||
336 Name == "MOVZX16rr8" ||
337 Name == "PUSH32i16" ||
338 Name == "PUSH64i16" ||
339 Name == "MOVPQI2QImr" ||
344 Name == "MMX_MOVD64rrv164" ||
345 Name == "CRC32m16" ||
346 Name == "MOV64ri64i32" ||
350 // Filter out instructions with segment override prefixes.
351 // They're too messy to handle now and we'll special case them if needed.
354 return FILTER_STRONG;
356 // Filter out instructions that can't be printed.
358 if (AsmString.size() == 0)
359 return FILTER_STRONG;
361 // Filter out instructions with subreg operands.
363 if (AsmString.find("subreg") != AsmString.npos)
364 return FILTER_STRONG;
366 if (HasFROperands && Name.find("MOV") != Name.npos &&
367 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
368 (Name.find("to") != Name.npos)))
371 // Filter out the intrinsic form of instructions that also have an llvm
372 // operator form. FIXME this is temporary.
373 if (Name.find("irm") != Name.npos ||
374 Name.find("irr") != Name.npos)
377 return FILTER_NORMAL;
380 void RecognizableInstr::handleOperand(
382 unsigned &operandIndex,
383 unsigned &physicalOperandIndex,
384 unsigned &numPhysicalOperands,
385 unsigned *operandMapping,
386 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
388 if (physicalOperandIndex >= numPhysicalOperands)
391 assert(physicalOperandIndex < numPhysicalOperands);
394 while (operandMapping[operandIndex] != operandIndex) {
395 Spec->operands[operandIndex].encoding = ENCODING_DUP;
396 Spec->operands[operandIndex].type =
397 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
401 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
403 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
405 Spec->operands[operandIndex].type = typeFromString(typeName,
411 ++physicalOperandIndex;
414 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
417 if (!Rec->isSubClassOf("X86Inst"))
422 Spec->filtered = true;
425 ShouldBeEmitted = false;
431 Spec->insnContext = insnContext();
433 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
435 unsigned operandIndex;
436 unsigned numOperands = OperandList.size();
437 unsigned numPhysicalOperands = 0;
439 // operandMapping maps from operands in OperandList to their originals.
440 // If operandMapping[i] != i, then the entry is a duplicate.
441 unsigned operandMapping[X86_MAX_OPERANDS];
443 bool hasFROperands = false;
445 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
447 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
448 if (OperandList[operandIndex].Constraints.size()) {
449 const CodeGenInstruction::ConstraintInfo &Constraint =
450 OperandList[operandIndex].Constraints[0];
451 if (Constraint.isTied()) {
452 operandMapping[operandIndex] = Constraint.getTiedOperand();
454 ++numPhysicalOperands;
455 operandMapping[operandIndex] = operandIndex;
458 ++numPhysicalOperands;
459 operandMapping[operandIndex] = operandIndex;
462 const std::string &recName = OperandList[operandIndex].Rec->getName();
464 if (recName.find("FR") != recName.npos)
465 hasFROperands = true;
468 if (hasFROperands && Name.find("MOV") != Name.npos &&
469 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
470 (Name.find("to") != Name.npos)))
471 ShouldBeEmitted = false;
473 if (!ShouldBeEmitted)
476 #define HANDLE_OPERAND(class) \
477 handleOperand(false, \
479 physicalOperandIndex, \
480 numPhysicalOperands, \
482 class##EncodingFromString);
484 #define HANDLE_OPTIONAL(class) \
485 handleOperand(true, \
487 physicalOperandIndex, \
488 numPhysicalOperands, \
490 class##EncodingFromString);
492 // operandIndex should always be < numOperands
494 // physicalOperandIndex should always be < numPhysicalOperands
495 unsigned physicalOperandIndex = 0;
498 case X86Local::RawFrm:
499 // Operand 1 (optional) is an address or immediate.
500 // Operand 2 (optional) is an immediate.
501 assert(numPhysicalOperands <= 2 &&
502 "Unexpected number of operands for RawFrm");
503 HANDLE_OPTIONAL(relocation)
504 HANDLE_OPTIONAL(immediate)
506 case X86Local::AddRegFrm:
507 // Operand 1 is added to the opcode.
508 // Operand 2 (optional) is an address.
509 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
510 "Unexpected number of operands for AddRegFrm");
511 HANDLE_OPERAND(opcodeModifier)
512 HANDLE_OPTIONAL(relocation)
514 case X86Local::MRMDestReg:
515 // Operand 1 is a register operand in the R/M field.
516 // Operand 2 is a register operand in the Reg/Opcode field.
517 // Operand 3 (optional) is an immediate.
518 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
519 "Unexpected number of operands for MRMDestRegFrm");
520 HANDLE_OPERAND(rmRegister)
521 HANDLE_OPERAND(roRegister)
522 HANDLE_OPTIONAL(immediate)
524 case X86Local::MRMDestMem:
525 // Operand 1 is a memory operand (possibly SIB-extended)
526 // Operand 2 is a register operand in the Reg/Opcode field.
527 // Operand 3 (optional) is an immediate.
528 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
529 "Unexpected number of operands for MRMDestMemFrm");
530 HANDLE_OPERAND(memory)
531 HANDLE_OPERAND(roRegister)
532 HANDLE_OPTIONAL(immediate)
534 case X86Local::MRMSrcReg:
535 // Operand 1 is a register operand in the Reg/Opcode field.
536 // Operand 2 is a register operand in the R/M field.
537 // Operand 3 (optional) is an immediate.
538 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
539 "Unexpected number of operands for MRMSrcRegFrm");
540 HANDLE_OPERAND(roRegister)
541 HANDLE_OPERAND(rmRegister)
544 // FIXME: In AVX, the register below becomes the one encoded
545 // in ModRMVEX and the one above the one in the VEX.VVVV field
546 HANDLE_OPTIONAL(rmRegister)
548 HANDLE_OPTIONAL(immediate)
550 case X86Local::MRMSrcMem:
551 // Operand 1 is a register operand in the Reg/Opcode field.
552 // Operand 2 is a memory operand (possibly SIB-extended)
553 // Operand 3 (optional) is an immediate.
554 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
555 "Unexpected number of operands for MRMSrcMemFrm");
556 HANDLE_OPERAND(roRegister)
559 // FIXME: In AVX, the register below becomes the one encoded
560 // in ModRMVEX and the one above the one in the VEX.VVVV field
561 HANDLE_OPTIONAL(rmRegister)
563 HANDLE_OPERAND(memory)
564 HANDLE_OPTIONAL(immediate)
566 case X86Local::MRM0r:
567 case X86Local::MRM1r:
568 case X86Local::MRM2r:
569 case X86Local::MRM3r:
570 case X86Local::MRM4r:
571 case X86Local::MRM5r:
572 case X86Local::MRM6r:
573 case X86Local::MRM7r:
574 // Operand 1 is a register operand in the R/M field.
575 // Operand 2 (optional) is an immediate or relocation.
576 assert(numPhysicalOperands <= 2 &&
577 "Unexpected number of operands for MRMnRFrm");
578 HANDLE_OPTIONAL(rmRegister)
579 HANDLE_OPTIONAL(relocation)
581 case X86Local::MRM0m:
582 case X86Local::MRM1m:
583 case X86Local::MRM2m:
584 case X86Local::MRM3m:
585 case X86Local::MRM4m:
586 case X86Local::MRM5m:
587 case X86Local::MRM6m:
588 case X86Local::MRM7m:
589 // Operand 1 is a memory operand (possibly SIB-extended)
590 // Operand 2 (optional) is an immediate or relocation.
591 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
592 "Unexpected number of operands for MRMnMFrm");
593 HANDLE_OPERAND(memory)
594 HANDLE_OPTIONAL(relocation)
596 case X86Local::MRMInitReg:
601 #undef HANDLE_OPERAND
602 #undef HANDLE_OPTIONAL
605 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
606 // Special cases where the LLVM tables are not complete
608 #define MAP(from, to) \
609 case X86Local::MRM_##from: \
610 filter = new ExactFilter(0x##from); \
613 OpcodeType opcodeType = (OpcodeType)-1;
615 ModRMFilter* filter = NULL;
616 uint8_t opcodeToSet = 0;
619 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
623 opcodeType = TWOBYTE;
627 if (needsModRMForDecode(Form))
628 filter = new ModFilter(isRegFormat(Form));
630 filter = new DumbFilter();
632 #define EXTENSION_TABLE(n) case 0x##n:
633 TWO_BYTE_EXTENSION_TABLES
634 #undef EXTENSION_TABLE
637 llvm_unreachable("Unhandled two-byte extended opcode");
638 case X86Local::MRM0r:
639 case X86Local::MRM1r:
640 case X86Local::MRM2r:
641 case X86Local::MRM3r:
642 case X86Local::MRM4r:
643 case X86Local::MRM5r:
644 case X86Local::MRM6r:
645 case X86Local::MRM7r:
646 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
648 case X86Local::MRM0m:
649 case X86Local::MRM1m:
650 case X86Local::MRM2m:
651 case X86Local::MRM3m:
652 case X86Local::MRM4m:
653 case X86Local::MRM5m:
654 case X86Local::MRM6m:
655 case X86Local::MRM7m:
656 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
662 opcodeToSet = Opcode;
665 opcodeType = THREEBYTE_38;
666 if (needsModRMForDecode(Form))
667 filter = new ModFilter(isRegFormat(Form));
669 filter = new DumbFilter();
670 opcodeToSet = Opcode;
673 opcodeType = THREEBYTE_3A;
674 if (needsModRMForDecode(Form))
675 filter = new ModFilter(isRegFormat(Form));
677 filter = new DumbFilter();
678 opcodeToSet = Opcode;
688 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
689 opcodeType = ONEBYTE;
690 if (Form == X86Local::AddRegFrm) {
691 Spec->modifierType = MODIFIER_MODRM;
692 Spec->modifierBase = Opcode;
693 filter = new AddRegEscapeFilter(Opcode);
695 filter = new EscapeFilter(true, Opcode);
697 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
700 opcodeType = ONEBYTE;
702 #define EXTENSION_TABLE(n) case 0x##n:
703 ONE_BYTE_EXTENSION_TABLES
704 #undef EXTENSION_TABLE
707 llvm_unreachable("Fell through the cracks of a single-byte "
709 case X86Local::MRM0r:
710 case X86Local::MRM1r:
711 case X86Local::MRM2r:
712 case X86Local::MRM3r:
713 case X86Local::MRM4r:
714 case X86Local::MRM5r:
715 case X86Local::MRM6r:
716 case X86Local::MRM7r:
717 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
719 case X86Local::MRM0m:
720 case X86Local::MRM1m:
721 case X86Local::MRM2m:
722 case X86Local::MRM3m:
723 case X86Local::MRM4m:
724 case X86Local::MRM5m:
725 case X86Local::MRM6m:
726 case X86Local::MRM7m:
727 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
740 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
743 if (needsModRMForDecode(Form))
744 filter = new ModFilter(isRegFormat(Form));
746 filter = new DumbFilter();
749 opcodeToSet = Opcode;
752 assert(opcodeType != (OpcodeType)-1 &&
753 "Opcode type not set");
754 assert(filter && "Filter not set");
756 if (Form == X86Local::AddRegFrm) {
757 if(Spec->modifierType != MODIFIER_MODRM) {
758 assert(opcodeToSet < 0xf9 &&
759 "Not enough room for all ADDREG_FRM operands");
761 uint8_t currentOpcode;
763 for (currentOpcode = opcodeToSet;
764 currentOpcode < opcodeToSet + 8;
766 tables.setTableFields(opcodeType,
772 Spec->modifierType = MODIFIER_OPCODE;
773 Spec->modifierBase = opcodeToSet;
775 // modifierBase was set where MODIFIER_MODRM was set
776 tables.setTableFields(opcodeType,
783 tables.setTableFields(opcodeType,
789 Spec->modifierType = MODIFIER_NONE;
790 Spec->modifierBase = opcodeToSet;
798 #define TYPE(str, type) if (s == str) return type;
799 OperandType RecognizableInstr::typeFromString(const std::string &s,
802 bool hasOpSizePrefix) {
804 // For SSE instructions, we ignore the OpSize prefix and force operand
806 TYPE("GR16", TYPE_R16)
807 TYPE("GR32", TYPE_R32)
808 TYPE("GR64", TYPE_R64)
811 // For instructions with a REX_W prefix, a declared 32-bit register encoding
813 TYPE("GR32", TYPE_R32)
815 if(!hasOpSizePrefix) {
816 // For instructions without an OpSize prefix, a declared 16-bit register or
817 // immediate encoding is special.
818 TYPE("GR16", TYPE_R16)
819 TYPE("i16imm", TYPE_IMM16)
821 TYPE("i16mem", TYPE_Mv)
822 TYPE("i16imm", TYPE_IMMv)
823 TYPE("i16i8imm", TYPE_IMMv)
824 TYPE("GR16", TYPE_Rv)
825 TYPE("i32mem", TYPE_Mv)
826 TYPE("i32imm", TYPE_IMMv)
827 TYPE("i32i8imm", TYPE_IMM32)
828 TYPE("GR32", TYPE_Rv)
829 TYPE("i64mem", TYPE_Mv)
830 TYPE("i64i32imm", TYPE_IMM64)
831 TYPE("i64i8imm", TYPE_IMM64)
832 TYPE("GR64", TYPE_R64)
833 TYPE("i8mem", TYPE_M8)
834 TYPE("i8imm", TYPE_IMM8)
836 TYPE("VR128", TYPE_XMM128)
837 TYPE("f128mem", TYPE_M128)
838 TYPE("f256mem", TYPE_M256)
839 TYPE("FR64", TYPE_XMM64)
840 TYPE("f64mem", TYPE_M64FP)
841 TYPE("sdmem", TYPE_M64FP)
842 TYPE("FR32", TYPE_XMM32)
843 TYPE("f32mem", TYPE_M32FP)
844 TYPE("ssmem", TYPE_M32FP)
846 TYPE("i128mem", TYPE_M128)
847 TYPE("i64i32imm_pcrel", TYPE_REL64)
848 TYPE("i16imm_pcrel", TYPE_REL16)
849 TYPE("i32imm_pcrel", TYPE_REL32)
850 TYPE("SSECC", TYPE_IMM3)
851 TYPE("brtarget", TYPE_RELv)
852 TYPE("brtarget8", TYPE_REL8)
853 TYPE("f80mem", TYPE_M80FP)
854 TYPE("lea32mem", TYPE_LEA)
855 TYPE("lea64_32mem", TYPE_LEA)
856 TYPE("lea64mem", TYPE_LEA)
857 TYPE("VR64", TYPE_MM64)
858 TYPE("i64imm", TYPE_IMMv)
859 TYPE("opaque32mem", TYPE_M1616)
860 TYPE("opaque48mem", TYPE_M1632)
861 TYPE("opaque80mem", TYPE_M1664)
862 TYPE("opaque512mem", TYPE_M512)
863 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
864 TYPE("DEBUG_REG", TYPE_DEBUGREG)
865 TYPE("CONTROL_REG", TYPE_CONTROLREG)
866 TYPE("offset8", TYPE_MOFFS8)
867 TYPE("offset16", TYPE_MOFFS16)
868 TYPE("offset32", TYPE_MOFFS32)
869 TYPE("offset64", TYPE_MOFFS64)
870 errs() << "Unhandled type string " << s << "\n";
871 llvm_unreachable("Unhandled type string");
875 #define ENCODING(str, encoding) if (s == str) return encoding;
876 OperandEncoding RecognizableInstr::immediateEncodingFromString
877 (const std::string &s,
878 bool hasOpSizePrefix) {
879 if(!hasOpSizePrefix) {
880 // For instructions without an OpSize prefix, a declared 16-bit register or
881 // immediate encoding is special.
882 ENCODING("i16imm", ENCODING_IW)
884 ENCODING("i32i8imm", ENCODING_IB)
885 ENCODING("SSECC", ENCODING_IB)
886 ENCODING("i16imm", ENCODING_Iv)
887 ENCODING("i16i8imm", ENCODING_IB)
888 ENCODING("i32imm", ENCODING_Iv)
889 ENCODING("i64i32imm", ENCODING_ID)
890 ENCODING("i64i8imm", ENCODING_IB)
891 ENCODING("i8imm", ENCODING_IB)
892 errs() << "Unhandled immediate encoding " << s << "\n";
893 llvm_unreachable("Unhandled immediate encoding");
896 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
897 (const std::string &s,
898 bool hasOpSizePrefix) {
899 ENCODING("GR16", ENCODING_RM)
900 ENCODING("GR32", ENCODING_RM)
901 ENCODING("GR64", ENCODING_RM)
902 ENCODING("GR8", ENCODING_RM)
903 ENCODING("VR128", ENCODING_RM)
904 ENCODING("FR64", ENCODING_RM)
905 ENCODING("FR32", ENCODING_RM)
906 ENCODING("VR64", ENCODING_RM)
907 errs() << "Unhandled R/M register encoding " << s << "\n";
908 llvm_unreachable("Unhandled R/M register encoding");
911 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
912 (const std::string &s,
913 bool hasOpSizePrefix) {
914 ENCODING("GR16", ENCODING_REG)
915 ENCODING("GR32", ENCODING_REG)
916 ENCODING("GR64", ENCODING_REG)
917 ENCODING("GR8", ENCODING_REG)
918 ENCODING("VR128", ENCODING_REG)
919 ENCODING("FR64", ENCODING_REG)
920 ENCODING("FR32", ENCODING_REG)
921 ENCODING("VR64", ENCODING_REG)
922 ENCODING("SEGMENT_REG", ENCODING_REG)
923 ENCODING("DEBUG_REG", ENCODING_REG)
924 ENCODING("CONTROL_REG", ENCODING_REG)
925 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
926 llvm_unreachable("Unhandled reg/opcode register encoding");
929 OperandEncoding RecognizableInstr::memoryEncodingFromString
930 (const std::string &s,
931 bool hasOpSizePrefix) {
932 ENCODING("i16mem", ENCODING_RM)
933 ENCODING("i32mem", ENCODING_RM)
934 ENCODING("i64mem", ENCODING_RM)
935 ENCODING("i8mem", ENCODING_RM)
936 ENCODING("ssmem", ENCODING_RM)
937 ENCODING("sdmem", ENCODING_RM)
938 ENCODING("f128mem", ENCODING_RM)
939 ENCODING("f256mem", ENCODING_RM)
940 ENCODING("f64mem", ENCODING_RM)
941 ENCODING("f32mem", ENCODING_RM)
942 ENCODING("i128mem", ENCODING_RM)
943 ENCODING("f80mem", ENCODING_RM)
944 ENCODING("lea32mem", ENCODING_RM)
945 ENCODING("lea64_32mem", ENCODING_RM)
946 ENCODING("lea64mem", ENCODING_RM)
947 ENCODING("opaque32mem", ENCODING_RM)
948 ENCODING("opaque48mem", ENCODING_RM)
949 ENCODING("opaque80mem", ENCODING_RM)
950 ENCODING("opaque512mem", ENCODING_RM)
951 errs() << "Unhandled memory encoding " << s << "\n";
952 llvm_unreachable("Unhandled memory encoding");
955 OperandEncoding RecognizableInstr::relocationEncodingFromString
956 (const std::string &s,
957 bool hasOpSizePrefix) {
958 if(!hasOpSizePrefix) {
959 // For instructions without an OpSize prefix, a declared 16-bit register or
960 // immediate encoding is special.
961 ENCODING("i16imm", ENCODING_IW)
963 ENCODING("i16imm", ENCODING_Iv)
964 ENCODING("i16i8imm", ENCODING_IB)
965 ENCODING("i32imm", ENCODING_Iv)
966 ENCODING("i32i8imm", ENCODING_IB)
967 ENCODING("i64i32imm", ENCODING_ID)
968 ENCODING("i64i8imm", ENCODING_IB)
969 ENCODING("i8imm", ENCODING_IB)
970 ENCODING("i64i32imm_pcrel", ENCODING_ID)
971 ENCODING("i16imm_pcrel", ENCODING_IW)
972 ENCODING("i32imm_pcrel", ENCODING_ID)
973 ENCODING("brtarget", ENCODING_Iv)
974 ENCODING("brtarget8", ENCODING_IB)
975 ENCODING("i64imm", ENCODING_IO)
976 ENCODING("offset8", ENCODING_Ia)
977 ENCODING("offset16", ENCODING_Ia)
978 ENCODING("offset32", ENCODING_Ia)
979 ENCODING("offset64", ENCODING_Ia)
980 errs() << "Unhandled relocation encoding " << s << "\n";
981 llvm_unreachable("Unhandled relocation encoding");
984 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
985 (const std::string &s,
986 bool hasOpSizePrefix) {
987 ENCODING("RST", ENCODING_I)
988 ENCODING("GR32", ENCODING_Rv)
989 ENCODING("GR64", ENCODING_RO)
990 ENCODING("GR16", ENCODING_Rv)
991 ENCODING("GR8", ENCODING_RB)
992 errs() << "Unhandled opcode modifier encoding " << s << "\n";
993 llvm_unreachable("Unhandled opcode modifier encoding");