1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 #define THREE_BYTE_38_EXTENSION_TABLES \
125 using namespace X86Disassembler;
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 /// ModR/M byte for the instruction to be properly decoded. For example, a
129 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
132 /// @param form - The form of the instruction.
133 /// @return - true if the form implies that a ModR/M byte is required, false
135 static bool needsModRMForDecode(uint8_t form) {
136 if (form == X86Local::MRMDestReg ||
137 form == X86Local::MRMDestMem ||
138 form == X86Local::MRMSrcReg ||
139 form == X86Local::MRMSrcMem ||
140 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 /// the ModR/M byte to be 0b11.
150 /// @param form - The form of the instruction.
151 /// @return - true if the form implies that Mod must be 0b11, false
153 static bool isRegFormat(uint8_t form) {
154 if (form == X86Local::MRMDestReg ||
155 form == X86Local::MRMSrcReg ||
156 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 /// Useful for switch statements and the like.
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return - The field, with the first bit in the BitsInit as the lowest
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169 int width = init.getNumBits();
171 assert(width <= 8 && "Field is too large for uint8_t!");
178 for (index = 0; index < width; index++) {
179 if (static_cast<BitInit*>(init.getBit(index))->getValue())
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 /// name of the field.
191 /// @param rec - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195 BitsInit* bits = rec->getValueAsBitsInit(name);
196 return byteFromBitsInit(*bits);
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200 const CodeGenInstruction &insn,
205 Name = Rec->getName();
206 Spec = &tables.specForUID(UID);
208 if (!Rec->isSubClassOf("X86Inst")) {
209 ShouldBeEmitted = false;
213 Prefix = byteFromRec(Rec, "Prefix");
214 Opcode = byteFromRec(Rec, "Opcode");
215 Form = byteFromRec(Rec, "FormBits");
216 SegOvr = byteFromRec(Rec, "SegOvrBits");
218 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
219 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
220 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
221 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
222 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
223 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
224 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
225 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
226 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
228 Name = Rec->getName();
229 AsmString = Rec->getValueAsString("AsmString");
231 Operands = &insn.Operands.OperandList;
233 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
234 (Name.find("CRC32") != Name.npos);
235 HasFROperands = hasFROperands();
236 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
238 // Check for 64-bit inst which does not require REX
241 // FIXME: Is there some better way to check for In64BitMode?
242 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
243 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
244 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
248 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
253 // FIXME: These instructions aren't marked as 64-bit in any way
254 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
255 Rec->getName() == "MASKMOVDQU64" ||
256 Rec->getName() == "POPFS64" ||
257 Rec->getName() == "POPGS64" ||
258 Rec->getName() == "PUSHFS64" ||
259 Rec->getName() == "PUSHGS64" ||
260 Rec->getName() == "REX64_PREFIX" ||
261 Rec->getName().find("MOV64") != Name.npos ||
262 Rec->getName().find("PUSH64") != Name.npos ||
263 Rec->getName().find("POP64") != Name.npos;
265 ShouldBeEmitted = true;
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 const CodeGenInstruction &insn,
272 // Ignore "asm parser only" instructions.
273 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
276 RecognizableInstr recogInstr(tables, insn, uid);
278 recogInstr.emitInstructionSpecifier(tables);
280 if (recogInstr.shouldBeEmitted())
281 recogInstr.emitDecodePath(tables);
284 InstructionContext RecognizableInstr::insnContext() const {
285 InstructionContext insnContext;
287 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
288 if (HasVEX_LPrefix && HasVEX_WPrefix)
289 llvm_unreachable("Don't support VEX.L and VEX.W together");
290 else if (HasOpSizePrefix && HasVEX_LPrefix)
291 insnContext = IC_VEX_L_OPSIZE;
292 else if (HasOpSizePrefix && HasVEX_WPrefix)
293 insnContext = IC_VEX_W_OPSIZE;
294 else if (HasOpSizePrefix)
295 insnContext = IC_VEX_OPSIZE;
296 else if (HasVEX_LPrefix &&
297 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
298 insnContext = IC_VEX_L_XS;
299 else if (HasVEX_LPrefix &&
300 (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
301 insnContext = IC_VEX_L_XD;
302 else if (HasVEX_WPrefix &&
303 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
304 insnContext = IC_VEX_W_XS;
305 else if (HasVEX_WPrefix &&
306 (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
307 insnContext = IC_VEX_W_XD;
308 else if (HasVEX_WPrefix)
309 insnContext = IC_VEX_W;
310 else if (HasVEX_LPrefix)
311 insnContext = IC_VEX_L;
312 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
313 insnContext = IC_VEX_XD;
314 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
315 insnContext = IC_VEX_XS;
317 insnContext = IC_VEX;
318 } else if (Is64Bit || HasREX_WPrefix) {
319 if (HasREX_WPrefix && HasOpSizePrefix)
320 insnContext = IC_64BIT_REXW_OPSIZE;
321 else if (HasOpSizePrefix &&
322 (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
323 insnContext = IC_64BIT_XD_OPSIZE;
324 else if (HasOpSizePrefix &&
325 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
326 insnContext = IC_64BIT_XS_OPSIZE;
327 else if (HasOpSizePrefix)
328 insnContext = IC_64BIT_OPSIZE;
329 else if (HasREX_WPrefix &&
330 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
331 insnContext = IC_64BIT_REXW_XS;
332 else if (HasREX_WPrefix &&
333 (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
334 insnContext = IC_64BIT_REXW_XD;
335 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
336 insnContext = IC_64BIT_XD;
337 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
338 insnContext = IC_64BIT_XS;
339 else if (HasREX_WPrefix)
340 insnContext = IC_64BIT_REXW;
342 insnContext = IC_64BIT;
344 if (HasOpSizePrefix &&
345 (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
346 insnContext = IC_XD_OPSIZE;
347 else if (HasOpSizePrefix &&
348 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
349 insnContext = IC_XS_OPSIZE;
350 else if (HasOpSizePrefix)
351 insnContext = IC_OPSIZE;
352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
354 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
355 Prefix == X86Local::REP)
364 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
369 // Filter out intrinsics
371 if (!Rec->isSubClassOf("X86Inst"))
372 return FILTER_STRONG;
374 if (Form == X86Local::Pseudo ||
375 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
376 return FILTER_STRONG;
378 if (Form == X86Local::MRMInitReg)
379 return FILTER_STRONG;
382 // Filter out artificial instructions
384 if (Name.find("TAILJMP") != Name.npos ||
385 Name.find("_Int") != Name.npos ||
386 Name.find("_int") != Name.npos ||
387 Name.find("Int_") != Name.npos ||
388 Name.find("_NOREX") != Name.npos ||
389 Name.find("_TC") != Name.npos ||
390 Name.find("EH_RETURN") != Name.npos ||
391 Name.find("V_SET") != Name.npos ||
392 Name.find("LOCK_") != Name.npos ||
393 Name.find("WIN") != Name.npos ||
394 Name.find("_AVX") != Name.npos ||
395 Name.find("2SDL") != Name.npos)
396 return FILTER_STRONG;
398 // Filter out instructions with segment override prefixes.
399 // They're too messy to handle now and we'll special case them if needed.
402 return FILTER_STRONG;
404 // Filter out instructions that can't be printed.
406 if (AsmString.size() == 0)
407 return FILTER_STRONG;
409 // Filter out instructions with subreg operands.
411 if (AsmString.find("subreg") != AsmString.npos)
412 return FILTER_STRONG;
419 // Filter out instructions with a LOCK prefix;
420 // prefer forms that do not have the prefix
424 // Filter out alternate forms of AVX instructions
425 if (Name.find("_alt") != Name.npos ||
426 Name.find("XrYr") != Name.npos ||
427 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
428 Name.find("_64mr") != Name.npos ||
429 Name.find("Xrr") != Name.npos ||
430 Name.find("rr64") != Name.npos)
433 if (Name == "VMASKMOVDQU64" ||
434 Name == "VEXTRACTPSrr64" ||
435 Name == "VMOVQd64rr" ||
436 Name == "VMOVQs64rr")
441 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
443 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
446 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
448 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
450 if (Name.find("Fs") != Name.npos)
452 if (Name == "MOVLPDrr" ||
453 Name == "MOVLPSrr" ||
459 Name == "MOVSX16rm8" ||
460 Name == "MOVSX16rr8" ||
461 Name == "MOVZX16rm8" ||
462 Name == "MOVZX16rr8" ||
463 Name == "PUSH32i16" ||
464 Name == "PUSH64i16" ||
465 Name == "MOVPQI2QImr" ||
466 Name == "VMOVPQI2QImr" ||
471 Name == "MMX_MOVD64rrv164" ||
472 Name == "CRC32m16" ||
473 Name == "MOV64ri64i32" ||
477 if (HasFROperands && Name.find("MOV") != Name.npos &&
478 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
479 (Name.find("to") != Name.npos)))
482 return FILTER_NORMAL;
485 bool RecognizableInstr::hasFROperands() const {
486 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
487 unsigned numOperands = OperandList.size();
489 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
490 const std::string &recName = OperandList[operandIndex].Rec->getName();
492 if (recName.find("FR") != recName.npos)
498 bool RecognizableInstr::has256BitOperands() const {
499 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
500 unsigned numOperands = OperandList.size();
502 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
503 const std::string &recName = OperandList[operandIndex].Rec->getName();
505 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
512 void RecognizableInstr::handleOperand(
514 unsigned &operandIndex,
515 unsigned &physicalOperandIndex,
516 unsigned &numPhysicalOperands,
517 unsigned *operandMapping,
518 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
520 if (physicalOperandIndex >= numPhysicalOperands)
523 assert(physicalOperandIndex < numPhysicalOperands);
526 while (operandMapping[operandIndex] != operandIndex) {
527 Spec->operands[operandIndex].encoding = ENCODING_DUP;
528 Spec->operands[operandIndex].type =
529 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
533 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
535 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
537 Spec->operands[operandIndex].type = typeFromString(typeName,
543 ++physicalOperandIndex;
546 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
549 if (!Rec->isSubClassOf("X86Inst"))
554 Spec->filtered = true;
557 ShouldBeEmitted = false;
563 Spec->insnContext = insnContext();
565 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
567 unsigned operandIndex;
568 unsigned numOperands = OperandList.size();
569 unsigned numPhysicalOperands = 0;
571 // operandMapping maps from operands in OperandList to their originals.
572 // If operandMapping[i] != i, then the entry is a duplicate.
573 unsigned operandMapping[X86_MAX_OPERANDS];
575 bool hasFROperands = false;
577 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
579 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
580 if (OperandList[operandIndex].Constraints.size()) {
581 const CGIOperandList::ConstraintInfo &Constraint =
582 OperandList[operandIndex].Constraints[0];
583 if (Constraint.isTied()) {
584 operandMapping[operandIndex] = Constraint.getTiedOperand();
586 ++numPhysicalOperands;
587 operandMapping[operandIndex] = operandIndex;
590 ++numPhysicalOperands;
591 operandMapping[operandIndex] = operandIndex;
594 const std::string &recName = OperandList[operandIndex].Rec->getName();
596 if (recName.find("FR") != recName.npos)
597 hasFROperands = true;
600 if (hasFROperands && Name.find("MOV") != Name.npos &&
601 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
602 (Name.find("to") != Name.npos)))
603 ShouldBeEmitted = false;
605 if (!ShouldBeEmitted)
608 #define HANDLE_OPERAND(class) \
609 handleOperand(false, \
611 physicalOperandIndex, \
612 numPhysicalOperands, \
614 class##EncodingFromString);
616 #define HANDLE_OPTIONAL(class) \
617 handleOperand(true, \
619 physicalOperandIndex, \
620 numPhysicalOperands, \
622 class##EncodingFromString);
624 // operandIndex should always be < numOperands
626 // physicalOperandIndex should always be < numPhysicalOperands
627 unsigned physicalOperandIndex = 0;
630 case X86Local::RawFrm:
631 // Operand 1 (optional) is an address or immediate.
632 // Operand 2 (optional) is an immediate.
633 assert(numPhysicalOperands <= 2 &&
634 "Unexpected number of operands for RawFrm");
635 HANDLE_OPTIONAL(relocation)
636 HANDLE_OPTIONAL(immediate)
638 case X86Local::AddRegFrm:
639 // Operand 1 is added to the opcode.
640 // Operand 2 (optional) is an address.
641 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
642 "Unexpected number of operands for AddRegFrm");
643 HANDLE_OPERAND(opcodeModifier)
644 HANDLE_OPTIONAL(relocation)
646 case X86Local::MRMDestReg:
647 // Operand 1 is a register operand in the R/M field.
648 // Operand 2 is a register operand in the Reg/Opcode field.
649 // - In AVX, there is a register operand in the VEX.vvvv field here -
650 // Operand 3 (optional) is an immediate.
652 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
653 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
655 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
656 "Unexpected number of operands for MRMDestRegFrm");
658 HANDLE_OPERAND(rmRegister)
661 // FIXME: In AVX, the register below becomes the one encoded
662 // in ModRMVEX and the one above the one in the VEX.VVVV field
663 HANDLE_OPERAND(vvvvRegister)
665 HANDLE_OPERAND(roRegister)
666 HANDLE_OPTIONAL(immediate)
668 case X86Local::MRMDestMem:
669 // Operand 1 is a memory operand (possibly SIB-extended)
670 // Operand 2 is a register operand in the Reg/Opcode field.
671 // - In AVX, there is a register operand in the VEX.vvvv field here -
672 // Operand 3 (optional) is an immediate.
674 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
675 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
677 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
678 "Unexpected number of operands for MRMDestMemFrm");
679 HANDLE_OPERAND(memory)
682 // FIXME: In AVX, the register below becomes the one encoded
683 // in ModRMVEX and the one above the one in the VEX.VVVV field
684 HANDLE_OPERAND(vvvvRegister)
686 HANDLE_OPERAND(roRegister)
687 HANDLE_OPTIONAL(immediate)
689 case X86Local::MRMSrcReg:
690 // Operand 1 is a register operand in the Reg/Opcode field.
691 // Operand 2 is a register operand in the R/M field.
692 // - In AVX, there is a register operand in the VEX.vvvv field here -
693 // Operand 3 (optional) is an immediate.
695 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
696 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
697 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
699 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
700 "Unexpected number of operands for MRMSrcRegFrm");
702 HANDLE_OPERAND(roRegister)
705 // FIXME: In AVX, the register below becomes the one encoded
706 // in ModRMVEX and the one above the one in the VEX.VVVV field
707 HANDLE_OPERAND(vvvvRegister)
709 HANDLE_OPERAND(rmRegister)
711 if (HasVEX_4VOp3Prefix)
712 HANDLE_OPERAND(vvvvRegister)
714 HANDLE_OPTIONAL(immediate)
716 case X86Local::MRMSrcMem:
717 // Operand 1 is a register operand in the Reg/Opcode field.
718 // Operand 2 is a memory operand (possibly SIB-extended)
719 // - In AVX, there is a register operand in the VEX.vvvv field here -
720 // Operand 3 (optional) is an immediate.
722 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
723 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
724 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
726 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
727 "Unexpected number of operands for MRMSrcMemFrm");
729 HANDLE_OPERAND(roRegister)
732 // FIXME: In AVX, the register below becomes the one encoded
733 // in ModRMVEX and the one above the one in the VEX.VVVV field
734 HANDLE_OPERAND(vvvvRegister)
736 HANDLE_OPERAND(memory)
738 if (HasVEX_4VOp3Prefix)
739 HANDLE_OPERAND(vvvvRegister)
741 HANDLE_OPTIONAL(immediate)
743 case X86Local::MRM0r:
744 case X86Local::MRM1r:
745 case X86Local::MRM2r:
746 case X86Local::MRM3r:
747 case X86Local::MRM4r:
748 case X86Local::MRM5r:
749 case X86Local::MRM6r:
750 case X86Local::MRM7r:
751 // Operand 1 is a register operand in the R/M field.
752 // Operand 2 (optional) is an immediate or relocation.
754 assert(numPhysicalOperands <= 3 &&
755 "Unexpected number of operands for MRMnRFrm with VEX_4V");
757 assert(numPhysicalOperands <= 2 &&
758 "Unexpected number of operands for MRMnRFrm");
760 HANDLE_OPERAND(vvvvRegister)
761 HANDLE_OPTIONAL(rmRegister)
762 HANDLE_OPTIONAL(relocation)
764 case X86Local::MRM0m:
765 case X86Local::MRM1m:
766 case X86Local::MRM2m:
767 case X86Local::MRM3m:
768 case X86Local::MRM4m:
769 case X86Local::MRM5m:
770 case X86Local::MRM6m:
771 case X86Local::MRM7m:
772 // Operand 1 is a memory operand (possibly SIB-extended)
773 // Operand 2 (optional) is an immediate or relocation.
775 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
776 "Unexpected number of operands for MRMnMFrm");
778 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
779 "Unexpected number of operands for MRMnMFrm");
781 HANDLE_OPERAND(vvvvRegister)
782 HANDLE_OPERAND(memory)
783 HANDLE_OPTIONAL(relocation)
785 case X86Local::RawFrmImm8:
786 // operand 1 is a 16-bit immediate
787 // operand 2 is an 8-bit immediate
788 assert(numPhysicalOperands == 2 &&
789 "Unexpected number of operands for X86Local::RawFrmImm8");
790 HANDLE_OPERAND(immediate)
791 HANDLE_OPERAND(immediate)
793 case X86Local::RawFrmImm16:
794 // operand 1 is a 16-bit immediate
795 // operand 2 is a 16-bit immediate
796 HANDLE_OPERAND(immediate)
797 HANDLE_OPERAND(immediate)
799 case X86Local::MRMInitReg:
804 #undef HANDLE_OPERAND
805 #undef HANDLE_OPTIONAL
808 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
809 // Special cases where the LLVM tables are not complete
811 #define MAP(from, to) \
812 case X86Local::MRM_##from: \
813 filter = new ExactFilter(0x##from); \
816 OpcodeType opcodeType = (OpcodeType)-1;
818 ModRMFilter* filter = NULL;
819 uint8_t opcodeToSet = 0;
822 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
826 opcodeType = TWOBYTE;
830 if (needsModRMForDecode(Form))
831 filter = new ModFilter(isRegFormat(Form));
833 filter = new DumbFilter();
835 #define EXTENSION_TABLE(n) case 0x##n:
836 TWO_BYTE_EXTENSION_TABLES
837 #undef EXTENSION_TABLE
840 llvm_unreachable("Unhandled two-byte extended opcode");
841 case X86Local::MRM0r:
842 case X86Local::MRM1r:
843 case X86Local::MRM2r:
844 case X86Local::MRM3r:
845 case X86Local::MRM4r:
846 case X86Local::MRM5r:
847 case X86Local::MRM6r:
848 case X86Local::MRM7r:
849 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
851 case X86Local::MRM0m:
852 case X86Local::MRM1m:
853 case X86Local::MRM2m:
854 case X86Local::MRM3m:
855 case X86Local::MRM4m:
856 case X86Local::MRM5m:
857 case X86Local::MRM6m:
858 case X86Local::MRM7m:
859 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
865 opcodeToSet = Opcode;
870 opcodeType = THREEBYTE_38;
873 if (needsModRMForDecode(Form))
874 filter = new ModFilter(isRegFormat(Form));
876 filter = new DumbFilter();
878 #define EXTENSION_TABLE(n) case 0x##n:
879 THREE_BYTE_38_EXTENSION_TABLES
880 #undef EXTENSION_TABLE
883 llvm_unreachable("Unhandled two-byte extended opcode");
884 case X86Local::MRM0r:
885 case X86Local::MRM1r:
886 case X86Local::MRM2r:
887 case X86Local::MRM3r:
888 case X86Local::MRM4r:
889 case X86Local::MRM5r:
890 case X86Local::MRM6r:
891 case X86Local::MRM7r:
892 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
894 case X86Local::MRM0m:
895 case X86Local::MRM1m:
896 case X86Local::MRM2m:
897 case X86Local::MRM3m:
898 case X86Local::MRM4m:
899 case X86Local::MRM5m:
900 case X86Local::MRM6m:
901 case X86Local::MRM7m:
902 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
908 opcodeToSet = Opcode;
911 opcodeType = THREEBYTE_3A;
912 if (needsModRMForDecode(Form))
913 filter = new ModFilter(isRegFormat(Form));
915 filter = new DumbFilter();
916 opcodeToSet = Opcode;
919 opcodeType = THREEBYTE_A6;
920 if (needsModRMForDecode(Form))
921 filter = new ModFilter(isRegFormat(Form));
923 filter = new DumbFilter();
924 opcodeToSet = Opcode;
927 opcodeType = THREEBYTE_A7;
928 if (needsModRMForDecode(Form))
929 filter = new ModFilter(isRegFormat(Form));
931 filter = new DumbFilter();
932 opcodeToSet = Opcode;
942 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
943 opcodeType = ONEBYTE;
944 if (Form == X86Local::AddRegFrm) {
945 Spec->modifierType = MODIFIER_MODRM;
946 Spec->modifierBase = Opcode;
947 filter = new AddRegEscapeFilter(Opcode);
949 filter = new EscapeFilter(true, Opcode);
951 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
955 opcodeType = ONEBYTE;
957 #define EXTENSION_TABLE(n) case 0x##n:
958 ONE_BYTE_EXTENSION_TABLES
959 #undef EXTENSION_TABLE
962 llvm_unreachable("Fell through the cracks of a single-byte "
964 case X86Local::MRM0r:
965 case X86Local::MRM1r:
966 case X86Local::MRM2r:
967 case X86Local::MRM3r:
968 case X86Local::MRM4r:
969 case X86Local::MRM5r:
970 case X86Local::MRM6r:
971 case X86Local::MRM7r:
972 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
974 case X86Local::MRM0m:
975 case X86Local::MRM1m:
976 case X86Local::MRM2m:
977 case X86Local::MRM3m:
978 case X86Local::MRM4m:
979 case X86Local::MRM5m:
980 case X86Local::MRM6m:
981 case X86Local::MRM7m:
982 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
995 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
998 if (needsModRMForDecode(Form))
999 filter = new ModFilter(isRegFormat(Form));
1001 filter = new DumbFilter();
1003 } // switch (Opcode)
1004 opcodeToSet = Opcode;
1005 } // switch (Prefix)
1007 assert(opcodeType != (OpcodeType)-1 &&
1008 "Opcode type not set");
1009 assert(filter && "Filter not set");
1011 if (Form == X86Local::AddRegFrm) {
1012 if(Spec->modifierType != MODIFIER_MODRM) {
1013 assert(opcodeToSet < 0xf9 &&
1014 "Not enough room for all ADDREG_FRM operands");
1016 uint8_t currentOpcode;
1018 for (currentOpcode = opcodeToSet;
1019 currentOpcode < opcodeToSet + 8;
1021 tables.setTableFields(opcodeType,
1025 UID, Is32Bit, IgnoresVEX_L);
1027 Spec->modifierType = MODIFIER_OPCODE;
1028 Spec->modifierBase = opcodeToSet;
1030 // modifierBase was set where MODIFIER_MODRM was set
1031 tables.setTableFields(opcodeType,
1035 UID, Is32Bit, IgnoresVEX_L);
1038 tables.setTableFields(opcodeType,
1042 UID, Is32Bit, IgnoresVEX_L);
1044 Spec->modifierType = MODIFIER_NONE;
1045 Spec->modifierBase = opcodeToSet;
1053 #define TYPE(str, type) if (s == str) return type;
1054 OperandType RecognizableInstr::typeFromString(const std::string &s,
1056 bool hasREX_WPrefix,
1057 bool hasOpSizePrefix) {
1059 // For SSE instructions, we ignore the OpSize prefix and force operand
1061 TYPE("GR16", TYPE_R16)
1062 TYPE("GR32", TYPE_R32)
1063 TYPE("GR64", TYPE_R64)
1065 if(hasREX_WPrefix) {
1066 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1068 TYPE("GR32", TYPE_R32)
1070 if(!hasOpSizePrefix) {
1071 // For instructions without an OpSize prefix, a declared 16-bit register or
1072 // immediate encoding is special.
1073 TYPE("GR16", TYPE_R16)
1074 TYPE("i16imm", TYPE_IMM16)
1076 TYPE("i16mem", TYPE_Mv)
1077 TYPE("i16imm", TYPE_IMMv)
1078 TYPE("i16i8imm", TYPE_IMMv)
1079 TYPE("GR16", TYPE_Rv)
1080 TYPE("i32mem", TYPE_Mv)
1081 TYPE("i32imm", TYPE_IMMv)
1082 TYPE("i32i8imm", TYPE_IMM32)
1083 TYPE("u32u8imm", TYPE_IMM32)
1084 TYPE("GR32", TYPE_Rv)
1085 TYPE("i64mem", TYPE_Mv)
1086 TYPE("i64i32imm", TYPE_IMM64)
1087 TYPE("i64i8imm", TYPE_IMM64)
1088 TYPE("GR64", TYPE_R64)
1089 TYPE("i8mem", TYPE_M8)
1090 TYPE("i8imm", TYPE_IMM8)
1091 TYPE("GR8", TYPE_R8)
1092 TYPE("VR128", TYPE_XMM128)
1093 TYPE("f128mem", TYPE_M128)
1094 TYPE("f256mem", TYPE_M256)
1095 TYPE("FR64", TYPE_XMM64)
1096 TYPE("f64mem", TYPE_M64FP)
1097 TYPE("sdmem", TYPE_M64FP)
1098 TYPE("FR32", TYPE_XMM32)
1099 TYPE("f32mem", TYPE_M32FP)
1100 TYPE("ssmem", TYPE_M32FP)
1101 TYPE("RST", TYPE_ST)
1102 TYPE("i128mem", TYPE_M128)
1103 TYPE("i256mem", TYPE_M256)
1104 TYPE("i64i32imm_pcrel", TYPE_REL64)
1105 TYPE("i16imm_pcrel", TYPE_REL16)
1106 TYPE("i32imm_pcrel", TYPE_REL32)
1107 TYPE("SSECC", TYPE_IMM3)
1108 TYPE("brtarget", TYPE_RELv)
1109 TYPE("uncondbrtarget", TYPE_RELv)
1110 TYPE("brtarget8", TYPE_REL8)
1111 TYPE("f80mem", TYPE_M80FP)
1112 TYPE("lea32mem", TYPE_LEA)
1113 TYPE("lea64_32mem", TYPE_LEA)
1114 TYPE("lea64mem", TYPE_LEA)
1115 TYPE("VR64", TYPE_MM64)
1116 TYPE("i64imm", TYPE_IMMv)
1117 TYPE("opaque32mem", TYPE_M1616)
1118 TYPE("opaque48mem", TYPE_M1632)
1119 TYPE("opaque80mem", TYPE_M1664)
1120 TYPE("opaque512mem", TYPE_M512)
1121 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1122 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1123 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1124 TYPE("offset8", TYPE_MOFFS8)
1125 TYPE("offset16", TYPE_MOFFS16)
1126 TYPE("offset32", TYPE_MOFFS32)
1127 TYPE("offset64", TYPE_MOFFS64)
1128 TYPE("VR256", TYPE_XMM256)
1129 TYPE("GR16_NOAX", TYPE_Rv)
1130 TYPE("GR32_NOAX", TYPE_Rv)
1131 TYPE("GR64_NOAX", TYPE_R64)
1132 errs() << "Unhandled type string " << s << "\n";
1133 llvm_unreachable("Unhandled type string");
1137 #define ENCODING(str, encoding) if (s == str) return encoding;
1138 OperandEncoding RecognizableInstr::immediateEncodingFromString
1139 (const std::string &s,
1140 bool hasOpSizePrefix) {
1141 if(!hasOpSizePrefix) {
1142 // For instructions without an OpSize prefix, a declared 16-bit register or
1143 // immediate encoding is special.
1144 ENCODING("i16imm", ENCODING_IW)
1146 ENCODING("i32i8imm", ENCODING_IB)
1147 ENCODING("u32u8imm", ENCODING_IB)
1148 ENCODING("SSECC", ENCODING_IB)
1149 ENCODING("i16imm", ENCODING_Iv)
1150 ENCODING("i16i8imm", ENCODING_IB)
1151 ENCODING("i32imm", ENCODING_Iv)
1152 ENCODING("i64i32imm", ENCODING_ID)
1153 ENCODING("i64i8imm", ENCODING_IB)
1154 ENCODING("i8imm", ENCODING_IB)
1155 // This is not a typo. Instructions like BLENDVPD put
1156 // register IDs in 8-bit immediates nowadays.
1157 ENCODING("VR256", ENCODING_IB)
1158 ENCODING("VR128", ENCODING_IB)
1159 errs() << "Unhandled immediate encoding " << s << "\n";
1160 llvm_unreachable("Unhandled immediate encoding");
1163 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1164 (const std::string &s,
1165 bool hasOpSizePrefix) {
1166 ENCODING("GR16", ENCODING_RM)
1167 ENCODING("GR32", ENCODING_RM)
1168 ENCODING("GR64", ENCODING_RM)
1169 ENCODING("GR8", ENCODING_RM)
1170 ENCODING("VR128", ENCODING_RM)
1171 ENCODING("FR64", ENCODING_RM)
1172 ENCODING("FR32", ENCODING_RM)
1173 ENCODING("VR64", ENCODING_RM)
1174 ENCODING("VR256", ENCODING_RM)
1175 errs() << "Unhandled R/M register encoding " << s << "\n";
1176 llvm_unreachable("Unhandled R/M register encoding");
1179 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1180 (const std::string &s,
1181 bool hasOpSizePrefix) {
1182 ENCODING("GR16", ENCODING_REG)
1183 ENCODING("GR32", ENCODING_REG)
1184 ENCODING("GR64", ENCODING_REG)
1185 ENCODING("GR8", ENCODING_REG)
1186 ENCODING("VR128", ENCODING_REG)
1187 ENCODING("FR64", ENCODING_REG)
1188 ENCODING("FR32", ENCODING_REG)
1189 ENCODING("VR64", ENCODING_REG)
1190 ENCODING("SEGMENT_REG", ENCODING_REG)
1191 ENCODING("DEBUG_REG", ENCODING_REG)
1192 ENCODING("CONTROL_REG", ENCODING_REG)
1193 ENCODING("VR256", ENCODING_REG)
1194 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1195 llvm_unreachable("Unhandled reg/opcode register encoding");
1198 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1199 (const std::string &s,
1200 bool hasOpSizePrefix) {
1201 ENCODING("GR32", ENCODING_VVVV)
1202 ENCODING("GR64", ENCODING_VVVV)
1203 ENCODING("FR32", ENCODING_VVVV)
1204 ENCODING("FR64", ENCODING_VVVV)
1205 ENCODING("VR128", ENCODING_VVVV)
1206 ENCODING("VR256", ENCODING_VVVV)
1207 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1208 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1211 OperandEncoding RecognizableInstr::memoryEncodingFromString
1212 (const std::string &s,
1213 bool hasOpSizePrefix) {
1214 ENCODING("i16mem", ENCODING_RM)
1215 ENCODING("i32mem", ENCODING_RM)
1216 ENCODING("i64mem", ENCODING_RM)
1217 ENCODING("i8mem", ENCODING_RM)
1218 ENCODING("ssmem", ENCODING_RM)
1219 ENCODING("sdmem", ENCODING_RM)
1220 ENCODING("f128mem", ENCODING_RM)
1221 ENCODING("f256mem", ENCODING_RM)
1222 ENCODING("f64mem", ENCODING_RM)
1223 ENCODING("f32mem", ENCODING_RM)
1224 ENCODING("i128mem", ENCODING_RM)
1225 ENCODING("i256mem", ENCODING_RM)
1226 ENCODING("f80mem", ENCODING_RM)
1227 ENCODING("lea32mem", ENCODING_RM)
1228 ENCODING("lea64_32mem", ENCODING_RM)
1229 ENCODING("lea64mem", ENCODING_RM)
1230 ENCODING("opaque32mem", ENCODING_RM)
1231 ENCODING("opaque48mem", ENCODING_RM)
1232 ENCODING("opaque80mem", ENCODING_RM)
1233 ENCODING("opaque512mem", ENCODING_RM)
1234 errs() << "Unhandled memory encoding " << s << "\n";
1235 llvm_unreachable("Unhandled memory encoding");
1238 OperandEncoding RecognizableInstr::relocationEncodingFromString
1239 (const std::string &s,
1240 bool hasOpSizePrefix) {
1241 if(!hasOpSizePrefix) {
1242 // For instructions without an OpSize prefix, a declared 16-bit register or
1243 // immediate encoding is special.
1244 ENCODING("i16imm", ENCODING_IW)
1246 ENCODING("i16imm", ENCODING_Iv)
1247 ENCODING("i16i8imm", ENCODING_IB)
1248 ENCODING("i32imm", ENCODING_Iv)
1249 ENCODING("i32i8imm", ENCODING_IB)
1250 ENCODING("i64i32imm", ENCODING_ID)
1251 ENCODING("i64i8imm", ENCODING_IB)
1252 ENCODING("i8imm", ENCODING_IB)
1253 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1254 ENCODING("i16imm_pcrel", ENCODING_IW)
1255 ENCODING("i32imm_pcrel", ENCODING_ID)
1256 ENCODING("brtarget", ENCODING_Iv)
1257 ENCODING("brtarget8", ENCODING_IB)
1258 ENCODING("i64imm", ENCODING_IO)
1259 ENCODING("offset8", ENCODING_Ia)
1260 ENCODING("offset16", ENCODING_Ia)
1261 ENCODING("offset32", ENCODING_Ia)
1262 ENCODING("offset64", ENCODING_Ia)
1263 errs() << "Unhandled relocation encoding " << s << "\n";
1264 llvm_unreachable("Unhandled relocation encoding");
1267 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1268 (const std::string &s,
1269 bool hasOpSizePrefix) {
1270 ENCODING("RST", ENCODING_I)
1271 ENCODING("GR32", ENCODING_Rv)
1272 ENCODING("GR64", ENCODING_RO)
1273 ENCODING("GR16", ENCODING_Rv)
1274 ENCODING("GR8", ENCODING_RB)
1275 ENCODING("GR16_NOAX", ENCODING_Rv)
1276 ENCODING("GR32_NOAX", ENCODING_Rv)
1277 ENCODING("GR64_NOAX", ENCODING_RO)
1278 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1279 llvm_unreachable("Unhandled opcode modifier encoding");