1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
53 // A clone of X86 since we can't depend on something that is generated.
63 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
64 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
65 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
66 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
70 #define MAP(from, to) MRM_##from = to,
79 D8 = 3, D9 = 4, DA = 5, DB = 6,
80 DC = 7, DD = 8, DE = 9, DF = 10,
83 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 using namespace X86Disassembler;
140 /// needsModRMForDecode - Indicates whether a particular instruction requires a
141 /// ModR/M byte for the instruction to be properly decoded. For example, a
142 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
145 /// @param form - The form of the instruction.
146 /// @return - true if the form implies that a ModR/M byte is required, false
148 static bool needsModRMForDecode(uint8_t form) {
149 if (form == X86Local::MRMDestReg ||
150 form == X86Local::MRMDestMem ||
151 form == X86Local::MRMSrcReg ||
152 form == X86Local::MRMSrcMem ||
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
154 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
160 /// isRegFormat - Indicates whether a particular form requires the Mod field of
161 /// the ModR/M byte to be 0b11.
163 /// @param form - The form of the instruction.
164 /// @return - true if the form implies that Mod must be 0b11, false
166 static bool isRegFormat(uint8_t form) {
167 if (form == X86Local::MRMDestReg ||
168 form == X86Local::MRMSrcReg ||
169 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
175 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
176 /// Useful for switch statements and the like.
178 /// @param init - A reference to the BitsInit to be decoded.
179 /// @return - The field, with the first bit in the BitsInit as the lowest
181 static uint8_t byteFromBitsInit(BitsInit &init) {
182 int width = init.getNumBits();
184 assert(width <= 8 && "Field is too large for uint8_t!");
191 for (index = 0; index < width; index++) {
192 if (static_cast<BitInit*>(init.getBit(index))->getValue())
201 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
202 /// name of the field.
204 /// @param rec - The record from which to extract the value.
205 /// @param name - The name of the field in the record.
206 /// @return - The field, as translated by byteFromBitsInit().
207 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
208 BitsInit* bits = rec->getValueAsBitsInit(name);
209 return byteFromBitsInit(*bits);
212 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
213 const CodeGenInstruction &insn,
218 Name = Rec->getName();
219 Spec = &tables.specForUID(UID);
221 if (!Rec->isSubClassOf("X86Inst")) {
222 ShouldBeEmitted = false;
226 Prefix = byteFromRec(Rec, "Prefix");
227 Opcode = byteFromRec(Rec, "Opcode");
228 Form = byteFromRec(Rec, "FormBits");
229 SegOvr = byteFromRec(Rec, "SegOvrBits");
231 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
232 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
233 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
234 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
235 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
236 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
237 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
238 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
239 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
240 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
241 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
242 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
243 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
244 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
245 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
247 Name = Rec->getName();
248 AsmString = Rec->getValueAsString("AsmString");
250 Operands = &insn.Operands.OperandList;
252 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
253 (Name.find("CRC32") != Name.npos);
254 HasFROperands = hasFROperands();
255 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
257 // Check for 64-bit inst which does not require REX
260 // FIXME: Is there some better way to check for In64BitMode?
261 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
262 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
263 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
267 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
272 // FIXME: These instructions aren't marked as 64-bit in any way
273 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
274 Rec->getName() == "MASKMOVDQU64" ||
275 Rec->getName() == "POPFS64" ||
276 Rec->getName() == "POPGS64" ||
277 Rec->getName() == "PUSHFS64" ||
278 Rec->getName() == "PUSHGS64" ||
279 Rec->getName() == "REX64_PREFIX" ||
280 Rec->getName().find("MOV64") != Name.npos ||
281 Rec->getName().find("PUSH64") != Name.npos ||
282 Rec->getName().find("POP64") != Name.npos;
284 ShouldBeEmitted = true;
287 void RecognizableInstr::processInstr(DisassemblerTables &tables,
288 const CodeGenInstruction &insn,
291 // Ignore "asm parser only" instructions.
292 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
295 RecognizableInstr recogInstr(tables, insn, uid);
297 recogInstr.emitInstructionSpecifier(tables);
299 if (recogInstr.shouldBeEmitted())
300 recogInstr.emitDecodePath(tables);
303 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
304 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
306 InstructionContext RecognizableInstr::insnContext() const {
307 InstructionContext insnContext;
310 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
312 sprintf(msg, "Don't support VEX.L if EVEX_L2 is enabled: %s", Name.c_str());
313 llvm_unreachable(msg);
316 if (HasVEX_LPrefix && HasVEX_WPrefix) {
318 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
319 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
320 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
321 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
322 Prefix == X86Local::TAXD)
323 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
325 insnContext = EVEX_KB(IC_EVEX_L_W);
326 } else if (HasVEX_LPrefix) {
329 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
330 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
331 insnContext = EVEX_KB(IC_EVEX_L_XS);
332 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
333 Prefix == X86Local::TAXD)
334 insnContext = EVEX_KB(IC_EVEX_L_XD);
336 insnContext = EVEX_KB(IC_EVEX_L);
338 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
341 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
342 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
343 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
344 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
345 Prefix == X86Local::TAXD)
346 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
348 insnContext = EVEX_KB(IC_EVEX_L2_W);
349 } else if (HasEVEX_L2Prefix) {
352 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
353 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD)
355 insnContext = EVEX_KB(IC_EVEX_L2_XD);
356 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
357 insnContext = EVEX_KB(IC_EVEX_L2_XS);
359 insnContext = EVEX_KB(IC_EVEX_L2);
361 else if (HasVEX_WPrefix) {
364 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
365 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
366 insnContext = EVEX_KB(IC_EVEX_W_XS);
367 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD)
369 insnContext = EVEX_KB(IC_EVEX_W_XD);
371 insnContext = EVEX_KB(IC_EVEX_W);
374 else if (HasOpSizePrefix)
375 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
376 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
377 Prefix == X86Local::TAXD)
378 insnContext = EVEX_KB(IC_EVEX_XD);
379 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
380 insnContext = EVEX_KB(IC_EVEX_XS);
382 insnContext = EVEX_KB(IC_EVEX);
384 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
385 if (HasVEX_LPrefix && HasVEX_WPrefix) {
387 insnContext = IC_VEX_L_W_OPSIZE;
388 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
389 insnContext = IC_VEX_L_W_XS;
390 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
391 Prefix == X86Local::TAXD)
392 insnContext = IC_VEX_L_W_XD;
394 insnContext = IC_VEX_L_W;
395 } else if (HasOpSizePrefix && HasVEX_LPrefix)
396 insnContext = IC_VEX_L_OPSIZE;
397 else if (HasOpSizePrefix && HasVEX_WPrefix)
398 insnContext = IC_VEX_W_OPSIZE;
399 else if (HasOpSizePrefix)
400 insnContext = IC_VEX_OPSIZE;
401 else if (HasVEX_LPrefix &&
402 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
403 insnContext = IC_VEX_L_XS;
404 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
405 Prefix == X86Local::T8XD ||
406 Prefix == X86Local::TAXD))
407 insnContext = IC_VEX_L_XD;
408 else if (HasVEX_WPrefix &&
409 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
410 insnContext = IC_VEX_W_XS;
411 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
412 Prefix == X86Local::T8XD ||
413 Prefix == X86Local::TAXD))
414 insnContext = IC_VEX_W_XD;
415 else if (HasVEX_WPrefix)
416 insnContext = IC_VEX_W;
417 else if (HasVEX_LPrefix)
418 insnContext = IC_VEX_L;
419 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
420 Prefix == X86Local::TAXD)
421 insnContext = IC_VEX_XD;
422 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
423 insnContext = IC_VEX_XS;
425 insnContext = IC_VEX;
426 } else if (Is64Bit || HasREX_WPrefix) {
427 if (HasREX_WPrefix && HasOpSizePrefix)
428 insnContext = IC_64BIT_REXW_OPSIZE;
429 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
430 Prefix == X86Local::T8XD ||
431 Prefix == X86Local::TAXD))
432 insnContext = IC_64BIT_XD_OPSIZE;
433 else if (HasOpSizePrefix &&
434 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
435 insnContext = IC_64BIT_XS_OPSIZE;
436 else if (HasOpSizePrefix)
437 insnContext = IC_64BIT_OPSIZE;
438 else if (HasAdSizePrefix)
439 insnContext = IC_64BIT_ADSIZE;
440 else if (HasREX_WPrefix &&
441 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
442 insnContext = IC_64BIT_REXW_XS;
443 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
444 Prefix == X86Local::T8XD ||
445 Prefix == X86Local::TAXD))
446 insnContext = IC_64BIT_REXW_XD;
447 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
448 Prefix == X86Local::TAXD)
449 insnContext = IC_64BIT_XD;
450 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
451 insnContext = IC_64BIT_XS;
452 else if (HasREX_WPrefix)
453 insnContext = IC_64BIT_REXW;
455 insnContext = IC_64BIT;
457 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
458 Prefix == X86Local::T8XD ||
459 Prefix == X86Local::TAXD))
460 insnContext = IC_XD_OPSIZE;
461 else if (HasOpSizePrefix &&
462 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
463 insnContext = IC_XS_OPSIZE;
464 else if (HasOpSizePrefix)
465 insnContext = IC_OPSIZE;
466 else if (HasAdSizePrefix)
467 insnContext = IC_ADSIZE;
468 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
469 Prefix == X86Local::TAXD)
471 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
472 Prefix == X86Local::REP)
481 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
486 // Filter out intrinsics
488 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
490 if (Form == X86Local::Pseudo ||
491 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
492 return FILTER_STRONG;
495 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
496 // printed as a separate "instruction".
498 if (Name.find("_Int") != Name.npos ||
499 Name.find("Int_") != Name.npos)
500 return FILTER_STRONG;
502 // Filter out instructions with segment override prefixes.
503 // They're too messy to handle now and we'll special case them if needed.
506 return FILTER_STRONG;
514 // Filter out instructions with a LOCK prefix;
515 // prefer forms that do not have the prefix
519 // Filter out alternate forms of AVX instructions
520 if (Name.find("_alt") != Name.npos ||
521 Name.find("XrYr") != Name.npos ||
522 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
523 Name.find("_64mr") != Name.npos ||
524 Name.find("Xrr") != Name.npos ||
525 Name.find("rr64") != Name.npos)
530 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
532 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
535 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
537 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
539 if (Name.find("Fs") != Name.npos)
541 if (Name == "PUSH64i16" ||
542 Name == "MOVPQI2QImr" ||
543 Name == "VMOVPQI2QImr" ||
544 Name == "MMX_MOVD64rrv164" ||
545 Name == "MOV64ri64i32" ||
546 Name == "VMASKMOVDQU64" ||
547 Name == "VEXTRACTPSrr64" ||
548 Name == "VMOVQd64rr" ||
549 Name == "VMOVQs64rr")
552 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
553 // For now, just prefer the REP versions.
554 if (Name == "XACQUIRE_PREFIX" ||
555 Name == "XRELEASE_PREFIX")
558 if (HasFROperands && Name.find("MOV") != Name.npos &&
559 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
560 (Name.find("to") != Name.npos)))
561 return FILTER_STRONG;
563 return FILTER_NORMAL;
566 bool RecognizableInstr::hasFROperands() const {
567 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
568 unsigned numOperands = OperandList.size();
570 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
571 const std::string &recName = OperandList[operandIndex].Rec->getName();
573 if (recName.find("FR") != recName.npos)
579 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
580 unsigned &physicalOperandIndex,
581 unsigned &numPhysicalOperands,
582 const unsigned *operandMapping,
583 OperandEncoding (*encodingFromString)
585 bool hasOpSizePrefix)) {
587 if (physicalOperandIndex >= numPhysicalOperands)
590 assert(physicalOperandIndex < numPhysicalOperands);
593 while (operandMapping[operandIndex] != operandIndex) {
594 Spec->operands[operandIndex].encoding = ENCODING_DUP;
595 Spec->operands[operandIndex].type =
596 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
600 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
602 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
604 Spec->operands[operandIndex].type = typeFromString(typeName,
610 ++physicalOperandIndex;
613 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
616 if (!ShouldBeEmitted)
621 Spec->filtered = true;
624 ShouldBeEmitted = false;
630 Spec->insnContext = insnContext();
632 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
634 unsigned numOperands = OperandList.size();
635 unsigned numPhysicalOperands = 0;
637 // operandMapping maps from operands in OperandList to their originals.
638 // If operandMapping[i] != i, then the entry is a duplicate.
639 unsigned operandMapping[X86_MAX_OPERANDS];
640 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
642 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
643 if (OperandList[operandIndex].Constraints.size()) {
644 const CGIOperandList::ConstraintInfo &Constraint =
645 OperandList[operandIndex].Constraints[0];
646 if (Constraint.isTied()) {
647 operandMapping[operandIndex] = operandIndex;
648 operandMapping[Constraint.getTiedOperand()] = operandIndex;
650 ++numPhysicalOperands;
651 operandMapping[operandIndex] = operandIndex;
654 ++numPhysicalOperands;
655 operandMapping[operandIndex] = operandIndex;
659 #define HANDLE_OPERAND(class) \
660 handleOperand(false, \
662 physicalOperandIndex, \
663 numPhysicalOperands, \
665 class##EncodingFromString);
667 #define HANDLE_OPTIONAL(class) \
668 handleOperand(true, \
670 physicalOperandIndex, \
671 numPhysicalOperands, \
673 class##EncodingFromString);
675 // operandIndex should always be < numOperands
676 unsigned operandIndex = 0;
677 // physicalOperandIndex should always be < numPhysicalOperands
678 unsigned physicalOperandIndex = 0;
681 case X86Local::RawFrm:
682 // Operand 1 (optional) is an address or immediate.
683 // Operand 2 (optional) is an immediate.
684 assert(numPhysicalOperands <= 2 &&
685 "Unexpected number of operands for RawFrm");
686 HANDLE_OPTIONAL(relocation)
687 HANDLE_OPTIONAL(immediate)
689 case X86Local::AddRegFrm:
690 // Operand 1 is added to the opcode.
691 // Operand 2 (optional) is an address.
692 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
693 "Unexpected number of operands for AddRegFrm");
694 HANDLE_OPERAND(opcodeModifier)
695 HANDLE_OPTIONAL(relocation)
697 case X86Local::MRMDestReg:
698 // Operand 1 is a register operand in the R/M field.
699 // Operand 2 is a register operand in the Reg/Opcode field.
700 // - In AVX, there is a register operand in the VEX.vvvv field here -
701 // Operand 3 (optional) is an immediate.
703 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
704 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
706 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
707 "Unexpected number of operands for MRMDestRegFrm");
709 HANDLE_OPERAND(rmRegister)
712 // FIXME: In AVX, the register below becomes the one encoded
713 // in ModRMVEX and the one above the one in the VEX.VVVV field
714 HANDLE_OPERAND(vvvvRegister)
716 HANDLE_OPERAND(roRegister)
717 HANDLE_OPTIONAL(immediate)
719 case X86Local::MRMDestMem:
720 // Operand 1 is a memory operand (possibly SIB-extended)
721 // Operand 2 is a register operand in the Reg/Opcode field.
722 // - In AVX, there is a register operand in the VEX.vvvv field here -
723 // Operand 3 (optional) is an immediate.
725 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
726 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
728 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
729 "Unexpected number of operands for MRMDestMemFrm");
730 HANDLE_OPERAND(memory)
733 HANDLE_OPERAND(writemaskRegister)
736 // FIXME: In AVX, the register below becomes the one encoded
737 // in ModRMVEX and the one above the one in the VEX.VVVV field
738 HANDLE_OPERAND(vvvvRegister)
740 HANDLE_OPERAND(roRegister)
741 HANDLE_OPTIONAL(immediate)
743 case X86Local::MRMSrcReg:
744 // Operand 1 is a register operand in the Reg/Opcode field.
745 // Operand 2 is a register operand in the R/M field.
746 // - In AVX, there is a register operand in the VEX.vvvv field here -
747 // Operand 3 (optional) is an immediate.
748 // Operand 4 (optional) is an immediate.
750 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
751 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
752 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
754 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
755 "Unexpected number of operands for MRMSrcRegFrm");
757 HANDLE_OPERAND(roRegister)
760 HANDLE_OPERAND(writemaskRegister)
763 // FIXME: In AVX, the register below becomes the one encoded
764 // in ModRMVEX and the one above the one in the VEX.VVVV field
765 HANDLE_OPERAND(vvvvRegister)
768 HANDLE_OPERAND(immediate)
770 HANDLE_OPERAND(rmRegister)
772 if (HasVEX_4VOp3Prefix)
773 HANDLE_OPERAND(vvvvRegister)
775 if (!HasMemOp4Prefix)
776 HANDLE_OPTIONAL(immediate)
777 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
778 HANDLE_OPTIONAL(immediate)
780 case X86Local::MRMSrcMem:
781 // Operand 1 is a register operand in the Reg/Opcode field.
782 // Operand 2 is a memory operand (possibly SIB-extended)
783 // - In AVX, there is a register operand in the VEX.vvvv field here -
784 // Operand 3 (optional) is an immediate.
786 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
787 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
788 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
790 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
791 "Unexpected number of operands for MRMSrcMemFrm");
793 HANDLE_OPERAND(roRegister)
796 HANDLE_OPERAND(writemaskRegister)
799 // FIXME: In AVX, the register below becomes the one encoded
800 // in ModRMVEX and the one above the one in the VEX.VVVV field
801 HANDLE_OPERAND(vvvvRegister)
804 HANDLE_OPERAND(immediate)
806 HANDLE_OPERAND(memory)
808 if (HasVEX_4VOp3Prefix)
809 HANDLE_OPERAND(vvvvRegister)
811 if (!HasMemOp4Prefix)
812 HANDLE_OPTIONAL(immediate)
813 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
815 case X86Local::MRM0r:
816 case X86Local::MRM1r:
817 case X86Local::MRM2r:
818 case X86Local::MRM3r:
819 case X86Local::MRM4r:
820 case X86Local::MRM5r:
821 case X86Local::MRM6r:
822 case X86Local::MRM7r:
823 // Operand 1 is a register operand in the R/M field.
824 // Operand 2 (optional) is an immediate or relocation.
825 // Operand 3 (optional) is an immediate.
827 assert(numPhysicalOperands <= 3 &&
828 "Unexpected number of operands for MRMnRFrm with VEX_4V");
830 assert(numPhysicalOperands <= 3 &&
831 "Unexpected number of operands for MRMnRFrm");
833 HANDLE_OPERAND(vvvvRegister)
834 HANDLE_OPTIONAL(rmRegister)
835 HANDLE_OPTIONAL(relocation)
836 HANDLE_OPTIONAL(immediate)
838 case X86Local::MRM0m:
839 case X86Local::MRM1m:
840 case X86Local::MRM2m:
841 case X86Local::MRM3m:
842 case X86Local::MRM4m:
843 case X86Local::MRM5m:
844 case X86Local::MRM6m:
845 case X86Local::MRM7m:
846 // Operand 1 is a memory operand (possibly SIB-extended)
847 // Operand 2 (optional) is an immediate or relocation.
849 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
850 "Unexpected number of operands for MRMnMFrm");
852 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
853 "Unexpected number of operands for MRMnMFrm");
855 HANDLE_OPERAND(vvvvRegister)
856 HANDLE_OPERAND(memory)
857 HANDLE_OPTIONAL(relocation)
859 case X86Local::RawFrmImm8:
860 // operand 1 is a 16-bit immediate
861 // operand 2 is an 8-bit immediate
862 assert(numPhysicalOperands == 2 &&
863 "Unexpected number of operands for X86Local::RawFrmImm8");
864 HANDLE_OPERAND(immediate)
865 HANDLE_OPERAND(immediate)
867 case X86Local::RawFrmImm16:
868 // operand 1 is a 16-bit immediate
869 // operand 2 is a 16-bit immediate
870 HANDLE_OPERAND(immediate)
871 HANDLE_OPERAND(immediate)
873 case X86Local::MRM_F8:
874 if (Opcode == 0xc6) {
875 assert(numPhysicalOperands == 1 &&
876 "Unexpected number of operands for X86Local::MRM_F8");
877 HANDLE_OPERAND(immediate)
878 } else if (Opcode == 0xc7) {
879 assert(numPhysicalOperands == 1 &&
880 "Unexpected number of operands for X86Local::MRM_F8");
881 HANDLE_OPERAND(relocation)
884 case X86Local::MRMInitReg:
889 #undef HANDLE_OPERAND
890 #undef HANDLE_OPTIONAL
893 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
894 // Special cases where the LLVM tables are not complete
896 #define MAP(from, to) \
897 case X86Local::MRM_##from: \
898 filter = new ExactFilter(0x##from); \
901 OpcodeType opcodeType = (OpcodeType)-1;
903 ModRMFilter* filter = NULL;
904 uint8_t opcodeToSet = 0;
907 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
911 opcodeType = TWOBYTE;
915 if (needsModRMForDecode(Form))
916 filter = new ModFilter(isRegFormat(Form));
918 filter = new DumbFilter();
920 #define EXTENSION_TABLE(n) case 0x##n:
921 TWO_BYTE_EXTENSION_TABLES
922 #undef EXTENSION_TABLE
925 llvm_unreachable("Unhandled two-byte extended opcode");
926 case X86Local::MRM0r:
927 case X86Local::MRM1r:
928 case X86Local::MRM2r:
929 case X86Local::MRM3r:
930 case X86Local::MRM4r:
931 case X86Local::MRM5r:
932 case X86Local::MRM6r:
933 case X86Local::MRM7r:
934 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
936 case X86Local::MRM0m:
937 case X86Local::MRM1m:
938 case X86Local::MRM2m:
939 case X86Local::MRM3m:
940 case X86Local::MRM4m:
941 case X86Local::MRM5m:
942 case X86Local::MRM6m:
943 case X86Local::MRM7m:
944 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
950 opcodeToSet = Opcode;
955 opcodeType = THREEBYTE_38;
958 if (needsModRMForDecode(Form))
959 filter = new ModFilter(isRegFormat(Form));
961 filter = new DumbFilter();
963 #define EXTENSION_TABLE(n) case 0x##n:
964 THREE_BYTE_38_EXTENSION_TABLES
965 #undef EXTENSION_TABLE
968 llvm_unreachable("Unhandled two-byte extended opcode");
969 case X86Local::MRM0r:
970 case X86Local::MRM1r:
971 case X86Local::MRM2r:
972 case X86Local::MRM3r:
973 case X86Local::MRM4r:
974 case X86Local::MRM5r:
975 case X86Local::MRM6r:
976 case X86Local::MRM7r:
977 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
979 case X86Local::MRM0m:
980 case X86Local::MRM1m:
981 case X86Local::MRM2m:
982 case X86Local::MRM3m:
983 case X86Local::MRM4m:
984 case X86Local::MRM5m:
985 case X86Local::MRM6m:
986 case X86Local::MRM7m:
987 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
993 opcodeToSet = Opcode;
997 opcodeType = THREEBYTE_3A;
998 if (needsModRMForDecode(Form))
999 filter = new ModFilter(isRegFormat(Form));
1001 filter = new DumbFilter();
1002 opcodeToSet = Opcode;
1005 opcodeType = THREEBYTE_A6;
1006 if (needsModRMForDecode(Form))
1007 filter = new ModFilter(isRegFormat(Form));
1009 filter = new DumbFilter();
1010 opcodeToSet = Opcode;
1013 opcodeType = THREEBYTE_A7;
1014 if (needsModRMForDecode(Form))
1015 filter = new ModFilter(isRegFormat(Form));
1017 filter = new DumbFilter();
1018 opcodeToSet = Opcode;
1028 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1029 opcodeType = ONEBYTE;
1030 if (Form == X86Local::AddRegFrm) {
1031 Spec->modifierType = MODIFIER_MODRM;
1032 Spec->modifierBase = Opcode;
1033 filter = new AddRegEscapeFilter(Opcode);
1035 filter = new EscapeFilter(true, Opcode);
1037 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1041 opcodeType = ONEBYTE;
1043 #define EXTENSION_TABLE(n) case 0x##n:
1044 ONE_BYTE_EXTENSION_TABLES
1045 #undef EXTENSION_TABLE
1048 llvm_unreachable("Fell through the cracks of a single-byte "
1050 case X86Local::MRM0r:
1051 case X86Local::MRM1r:
1052 case X86Local::MRM2r:
1053 case X86Local::MRM3r:
1054 case X86Local::MRM4r:
1055 case X86Local::MRM5r:
1056 case X86Local::MRM6r:
1057 case X86Local::MRM7r:
1058 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1060 case X86Local::MRM0m:
1061 case X86Local::MRM1m:
1062 case X86Local::MRM2m:
1063 case X86Local::MRM3m:
1064 case X86Local::MRM4m:
1065 case X86Local::MRM5m:
1066 case X86Local::MRM6m:
1067 case X86Local::MRM7m:
1068 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1081 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1084 if (needsModRMForDecode(Form))
1085 filter = new ModFilter(isRegFormat(Form));
1087 filter = new DumbFilter();
1089 } // switch (Opcode)
1090 opcodeToSet = Opcode;
1091 } // switch (Prefix)
1093 assert(opcodeType != (OpcodeType)-1 &&
1094 "Opcode type not set");
1095 assert(filter && "Filter not set");
1097 if (Form == X86Local::AddRegFrm) {
1098 if(Spec->modifierType != MODIFIER_MODRM) {
1099 assert(opcodeToSet < 0xf9 &&
1100 "Not enough room for all ADDREG_FRM operands");
1102 uint8_t currentOpcode;
1104 for (currentOpcode = opcodeToSet;
1105 currentOpcode < opcodeToSet + 8;
1107 tables.setTableFields(opcodeType,
1111 UID, Is32Bit, IgnoresVEX_L);
1113 Spec->modifierType = MODIFIER_OPCODE;
1114 Spec->modifierBase = opcodeToSet;
1116 // modifierBase was set where MODIFIER_MODRM was set
1117 tables.setTableFields(opcodeType,
1121 UID, Is32Bit, IgnoresVEX_L);
1124 tables.setTableFields(opcodeType,
1128 UID, Is32Bit, IgnoresVEX_L);
1130 Spec->modifierType = MODIFIER_NONE;
1131 Spec->modifierBase = opcodeToSet;
1139 #define TYPE(str, type) if (s == str) return type;
1140 OperandType RecognizableInstr::typeFromString(const std::string &s,
1142 bool hasREX_WPrefix,
1143 bool hasOpSizePrefix) {
1145 // For SSE instructions, we ignore the OpSize prefix and force operand
1147 TYPE("GR16", TYPE_R16)
1148 TYPE("GR32", TYPE_R32)
1149 TYPE("GR64", TYPE_R64)
1151 if(hasREX_WPrefix) {
1152 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1154 TYPE("GR32", TYPE_R32)
1156 if(!hasOpSizePrefix) {
1157 // For instructions without an OpSize prefix, a declared 16-bit register or
1158 // immediate encoding is special.
1159 TYPE("GR16", TYPE_R16)
1160 TYPE("i16imm", TYPE_IMM16)
1162 TYPE("i16mem", TYPE_Mv)
1163 TYPE("i16imm", TYPE_IMMv)
1164 TYPE("i16i8imm", TYPE_IMMv)
1165 TYPE("GR16", TYPE_Rv)
1166 TYPE("i32mem", TYPE_Mv)
1167 TYPE("i32imm", TYPE_IMMv)
1168 TYPE("i32i8imm", TYPE_IMM32)
1169 TYPE("u32u8imm", TYPE_IMM32)
1170 TYPE("GR32", TYPE_Rv)
1171 TYPE("i64mem", TYPE_Mv)
1172 TYPE("i64i32imm", TYPE_IMM64)
1173 TYPE("i64i8imm", TYPE_IMM64)
1174 TYPE("GR64", TYPE_R64)
1175 TYPE("i8mem", TYPE_M8)
1176 TYPE("i8imm", TYPE_IMM8)
1177 TYPE("GR8", TYPE_R8)
1178 TYPE("VR128", TYPE_XMM128)
1179 TYPE("VR128X", TYPE_XMM128)
1180 TYPE("f128mem", TYPE_M128)
1181 TYPE("f256mem", TYPE_M256)
1182 TYPE("f512mem", TYPE_M512)
1183 TYPE("FR64", TYPE_XMM64)
1184 TYPE("FR64X", TYPE_XMM64)
1185 TYPE("f64mem", TYPE_M64FP)
1186 TYPE("sdmem", TYPE_M64FP)
1187 TYPE("FR32", TYPE_XMM32)
1188 TYPE("FR32X", TYPE_XMM32)
1189 TYPE("f32mem", TYPE_M32FP)
1190 TYPE("ssmem", TYPE_M32FP)
1191 TYPE("RST", TYPE_ST)
1192 TYPE("i128mem", TYPE_M128)
1193 TYPE("i256mem", TYPE_M256)
1194 TYPE("i512mem", TYPE_M512)
1195 TYPE("i64i32imm_pcrel", TYPE_REL64)
1196 TYPE("i16imm_pcrel", TYPE_REL16)
1197 TYPE("i32imm_pcrel", TYPE_REL32)
1198 TYPE("SSECC", TYPE_IMM3)
1199 TYPE("AVXCC", TYPE_IMM5)
1200 TYPE("brtarget", TYPE_RELv)
1201 TYPE("uncondbrtarget", TYPE_RELv)
1202 TYPE("brtarget8", TYPE_REL8)
1203 TYPE("f80mem", TYPE_M80FP)
1204 TYPE("lea32mem", TYPE_LEA)
1205 TYPE("lea64_32mem", TYPE_LEA)
1206 TYPE("lea64mem", TYPE_LEA)
1207 TYPE("VR64", TYPE_MM64)
1208 TYPE("i64imm", TYPE_IMMv)
1209 TYPE("opaque32mem", TYPE_M1616)
1210 TYPE("opaque48mem", TYPE_M1632)
1211 TYPE("opaque80mem", TYPE_M1664)
1212 TYPE("opaque512mem", TYPE_M512)
1213 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1214 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1215 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1216 TYPE("offset8", TYPE_MOFFS8)
1217 TYPE("offset16", TYPE_MOFFS16)
1218 TYPE("offset32", TYPE_MOFFS32)
1219 TYPE("offset64", TYPE_MOFFS64)
1220 TYPE("VR256", TYPE_XMM256)
1221 TYPE("VR256X", TYPE_XMM256)
1222 TYPE("VR512", TYPE_XMM512)
1223 TYPE("VK8", TYPE_VK8)
1224 TYPE("VK8WM", TYPE_VK8)
1225 TYPE("VK16", TYPE_VK16)
1226 TYPE("VK16WM", TYPE_VK16)
1227 TYPE("GR16_NOAX", TYPE_Rv)
1228 TYPE("GR32_NOAX", TYPE_Rv)
1229 TYPE("GR64_NOAX", TYPE_R64)
1230 TYPE("vx32mem", TYPE_M32)
1231 TYPE("vy32mem", TYPE_M32)
1232 TYPE("vz32mem", TYPE_M32)
1233 TYPE("vx64mem", TYPE_M64)
1234 TYPE("vy64mem", TYPE_M64)
1235 TYPE("vy64xmem", TYPE_M64)
1236 TYPE("vz64mem", TYPE_M64)
1237 errs() << "Unhandled type string " << s << "\n";
1238 llvm_unreachable("Unhandled type string");
1242 #define ENCODING(str, encoding) if (s == str) return encoding;
1243 OperandEncoding RecognizableInstr::immediateEncodingFromString
1244 (const std::string &s,
1245 bool hasOpSizePrefix) {
1246 if(!hasOpSizePrefix) {
1247 // For instructions without an OpSize prefix, a declared 16-bit register or
1248 // immediate encoding is special.
1249 ENCODING("i16imm", ENCODING_IW)
1251 ENCODING("i32i8imm", ENCODING_IB)
1252 ENCODING("u32u8imm", ENCODING_IB)
1253 ENCODING("SSECC", ENCODING_IB)
1254 ENCODING("AVXCC", ENCODING_IB)
1255 ENCODING("i16imm", ENCODING_Iv)
1256 ENCODING("i16i8imm", ENCODING_IB)
1257 ENCODING("i32imm", ENCODING_Iv)
1258 ENCODING("i64i32imm", ENCODING_ID)
1259 ENCODING("i64i8imm", ENCODING_IB)
1260 ENCODING("i8imm", ENCODING_IB)
1261 // This is not a typo. Instructions like BLENDVPD put
1262 // register IDs in 8-bit immediates nowadays.
1263 ENCODING("FR32", ENCODING_IB)
1264 ENCODING("FR64", ENCODING_IB)
1265 ENCODING("VR128", ENCODING_IB)
1266 ENCODING("VR256", ENCODING_IB)
1267 ENCODING("FR32X", ENCODING_IB)
1268 ENCODING("FR64X", ENCODING_IB)
1269 ENCODING("VR128X", ENCODING_IB)
1270 ENCODING("VR256X", ENCODING_IB)
1271 ENCODING("VR512", ENCODING_IB)
1272 errs() << "Unhandled immediate encoding " << s << "\n";
1273 llvm_unreachable("Unhandled immediate encoding");
1276 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1277 (const std::string &s,
1278 bool hasOpSizePrefix) {
1279 ENCODING("GR16", ENCODING_RM)
1280 ENCODING("GR32", ENCODING_RM)
1281 ENCODING("GR64", ENCODING_RM)
1282 ENCODING("GR8", ENCODING_RM)
1283 ENCODING("VR128", ENCODING_RM)
1284 ENCODING("VR128X", ENCODING_RM)
1285 ENCODING("FR64", ENCODING_RM)
1286 ENCODING("FR32", ENCODING_RM)
1287 ENCODING("FR64X", ENCODING_RM)
1288 ENCODING("FR32X", ENCODING_RM)
1289 ENCODING("VR64", ENCODING_RM)
1290 ENCODING("VR256", ENCODING_RM)
1291 ENCODING("VR256X", ENCODING_RM)
1292 ENCODING("VR512", ENCODING_RM)
1293 ENCODING("VK8", ENCODING_RM)
1294 ENCODING("VK16", ENCODING_RM)
1295 errs() << "Unhandled R/M register encoding " << s << "\n";
1296 llvm_unreachable("Unhandled R/M register encoding");
1299 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1300 (const std::string &s,
1301 bool hasOpSizePrefix) {
1302 ENCODING("GR16", ENCODING_REG)
1303 ENCODING("GR32", ENCODING_REG)
1304 ENCODING("GR64", ENCODING_REG)
1305 ENCODING("GR8", ENCODING_REG)
1306 ENCODING("VR128", ENCODING_REG)
1307 ENCODING("FR64", ENCODING_REG)
1308 ENCODING("FR32", ENCODING_REG)
1309 ENCODING("VR64", ENCODING_REG)
1310 ENCODING("SEGMENT_REG", ENCODING_REG)
1311 ENCODING("DEBUG_REG", ENCODING_REG)
1312 ENCODING("CONTROL_REG", ENCODING_REG)
1313 ENCODING("VR256", ENCODING_REG)
1314 ENCODING("VR256X", ENCODING_REG)
1315 ENCODING("VR128X", ENCODING_REG)
1316 ENCODING("FR64X", ENCODING_REG)
1317 ENCODING("FR32X", ENCODING_REG)
1318 ENCODING("VR512", ENCODING_REG)
1319 ENCODING("VK8", ENCODING_REG)
1320 ENCODING("VK16", ENCODING_REG)
1321 ENCODING("VK8WM", ENCODING_REG)
1322 ENCODING("VK16WM", ENCODING_REG)
1323 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1324 llvm_unreachable("Unhandled reg/opcode register encoding");
1327 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1328 (const std::string &s,
1329 bool hasOpSizePrefix) {
1330 ENCODING("GR32", ENCODING_VVVV)
1331 ENCODING("GR64", ENCODING_VVVV)
1332 ENCODING("FR32", ENCODING_VVVV)
1333 ENCODING("FR64", ENCODING_VVVV)
1334 ENCODING("VR128", ENCODING_VVVV)
1335 ENCODING("VR256", ENCODING_VVVV)
1336 ENCODING("FR32X", ENCODING_VVVV)
1337 ENCODING("FR64X", ENCODING_VVVV)
1338 ENCODING("VR128X", ENCODING_VVVV)
1339 ENCODING("VR256X", ENCODING_VVVV)
1340 ENCODING("VR512", ENCODING_VVVV)
1341 ENCODING("VK8", ENCODING_VVVV)
1342 ENCODING("VK16", ENCODING_VVVV)
1343 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1344 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1347 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1348 (const std::string &s,
1349 bool hasOpSizePrefix) {
1350 ENCODING("VK8WM", ENCODING_WRITEMASK)
1351 ENCODING("VK16WM", ENCODING_WRITEMASK)
1352 errs() << "Unhandled mask register encoding " << s << "\n";
1353 llvm_unreachable("Unhandled mask register encoding");
1356 OperandEncoding RecognizableInstr::memoryEncodingFromString
1357 (const std::string &s,
1358 bool hasOpSizePrefix) {
1359 ENCODING("i16mem", ENCODING_RM)
1360 ENCODING("i32mem", ENCODING_RM)
1361 ENCODING("i64mem", ENCODING_RM)
1362 ENCODING("i8mem", ENCODING_RM)
1363 ENCODING("ssmem", ENCODING_RM)
1364 ENCODING("sdmem", ENCODING_RM)
1365 ENCODING("f128mem", ENCODING_RM)
1366 ENCODING("f256mem", ENCODING_RM)
1367 ENCODING("f512mem", ENCODING_RM)
1368 ENCODING("f64mem", ENCODING_RM)
1369 ENCODING("f32mem", ENCODING_RM)
1370 ENCODING("i128mem", ENCODING_RM)
1371 ENCODING("i256mem", ENCODING_RM)
1372 ENCODING("i512mem", ENCODING_RM)
1373 ENCODING("f80mem", ENCODING_RM)
1374 ENCODING("lea32mem", ENCODING_RM)
1375 ENCODING("lea64_32mem", ENCODING_RM)
1376 ENCODING("lea64mem", ENCODING_RM)
1377 ENCODING("opaque32mem", ENCODING_RM)
1378 ENCODING("opaque48mem", ENCODING_RM)
1379 ENCODING("opaque80mem", ENCODING_RM)
1380 ENCODING("opaque512mem", ENCODING_RM)
1381 ENCODING("vx32mem", ENCODING_RM)
1382 ENCODING("vy32mem", ENCODING_RM)
1383 ENCODING("vz32mem", ENCODING_RM)
1384 ENCODING("vx64mem", ENCODING_RM)
1385 ENCODING("vy64mem", ENCODING_RM)
1386 ENCODING("vy64xmem", ENCODING_RM)
1387 ENCODING("vz64mem", ENCODING_RM)
1388 errs() << "Unhandled memory encoding " << s << "\n";
1389 llvm_unreachable("Unhandled memory encoding");
1392 OperandEncoding RecognizableInstr::relocationEncodingFromString
1393 (const std::string &s,
1394 bool hasOpSizePrefix) {
1395 if(!hasOpSizePrefix) {
1396 // For instructions without an OpSize prefix, a declared 16-bit register or
1397 // immediate encoding is special.
1398 ENCODING("i16imm", ENCODING_IW)
1400 ENCODING("i16imm", ENCODING_Iv)
1401 ENCODING("i16i8imm", ENCODING_IB)
1402 ENCODING("i32imm", ENCODING_Iv)
1403 ENCODING("i32i8imm", ENCODING_IB)
1404 ENCODING("i64i32imm", ENCODING_ID)
1405 ENCODING("i64i8imm", ENCODING_IB)
1406 ENCODING("i8imm", ENCODING_IB)
1407 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1408 ENCODING("i16imm_pcrel", ENCODING_IW)
1409 ENCODING("i32imm_pcrel", ENCODING_ID)
1410 ENCODING("brtarget", ENCODING_Iv)
1411 ENCODING("brtarget8", ENCODING_IB)
1412 ENCODING("i64imm", ENCODING_IO)
1413 ENCODING("offset8", ENCODING_Ia)
1414 ENCODING("offset16", ENCODING_Ia)
1415 ENCODING("offset32", ENCODING_Ia)
1416 ENCODING("offset64", ENCODING_Ia)
1417 errs() << "Unhandled relocation encoding " << s << "\n";
1418 llvm_unreachable("Unhandled relocation encoding");
1421 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1422 (const std::string &s,
1423 bool hasOpSizePrefix) {
1424 ENCODING("RST", ENCODING_I)
1425 ENCODING("GR32", ENCODING_Rv)
1426 ENCODING("GR64", ENCODING_RO)
1427 ENCODING("GR16", ENCODING_Rv)
1428 ENCODING("GR8", ENCODING_RB)
1429 ENCODING("GR16_NOAX", ENCODING_Rv)
1430 ENCODING("GR32_NOAX", ENCODING_Rv)
1431 ENCODING("GR64_NOAX", ENCODING_RO)
1432 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1433 llvm_unreachable("Unhandled opcode modifier encoding");