1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, TF = 17
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 using namespace X86Disassembler;
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 /// ModR/M byte for the instruction to be properly decoded. For example, a
126 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
129 /// @param form - The form of the instruction.
130 /// @return - true if the form implies that a ModR/M byte is required, false
132 static bool needsModRMForDecode(uint8_t form) {
133 if (form == X86Local::MRMDestReg ||
134 form == X86Local::MRMDestMem ||
135 form == X86Local::MRMSrcReg ||
136 form == X86Local::MRMSrcMem ||
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 /// the ModR/M byte to be 0b11.
147 /// @param form - The form of the instruction.
148 /// @return - true if the form implies that Mod must be 0b11, false
150 static bool isRegFormat(uint8_t form) {
151 if (form == X86Local::MRMDestReg ||
152 form == X86Local::MRMSrcReg ||
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 /// Useful for switch statements and the like.
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return - The field, with the first bit in the BitsInit as the lowest
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166 int width = init.getNumBits();
168 assert(width <= 8 && "Field is too large for uint8_t!");
175 for (index = 0; index < width; index++) {
176 if (static_cast<BitInit*>(init.getBit(index))->getValue())
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 /// name of the field.
188 /// @param rec - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192 BitsInit* bits = rec->getValueAsBitsInit(name);
193 return byteFromBitsInit(*bits);
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197 const CodeGenInstruction &insn,
202 Name = Rec->getName();
203 Spec = &tables.specForUID(UID);
205 if (!Rec->isSubClassOf("X86Inst")) {
206 ShouldBeEmitted = false;
210 Prefix = byteFromRec(Rec, "Prefix");
211 Opcode = byteFromRec(Rec, "Opcode");
212 Form = byteFromRec(Rec, "FormBits");
213 SegOvr = byteFromRec(Rec, "SegOvrBits");
215 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
216 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
217 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
218 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
219 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
220 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
221 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
223 Name = Rec->getName();
224 AsmString = Rec->getValueAsString("AsmString");
226 Operands = &insn.Operands.OperandList;
228 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
229 HasFROperands = hasFROperands();
230 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
232 // Check for 64-bit inst which does not require REX
234 // FIXME: Is there some better way to check for In64BitMode?
235 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
236 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
237 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
242 // FIXME: These instructions aren't marked as 64-bit in any way
243 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
244 Rec->getName() == "MASKMOVDQU64" ||
245 Rec->getName() == "POPFS64" ||
246 Rec->getName() == "POPGS64" ||
247 Rec->getName() == "PUSHFS64" ||
248 Rec->getName() == "PUSHGS64" ||
249 Rec->getName() == "REX64_PREFIX" ||
250 Rec->getName().find("VMREAD64") != Name.npos ||
251 Rec->getName().find("VMWRITE64") != Name.npos ||
252 Rec->getName().find("MOV64") != Name.npos ||
253 Rec->getName().find("PUSH64") != Name.npos ||
254 Rec->getName().find("POP64") != Name.npos;
256 ShouldBeEmitted = true;
259 void RecognizableInstr::processInstr(DisassemblerTables &tables,
260 const CodeGenInstruction &insn,
263 // Ignore "asm parser only" instructions.
264 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
267 RecognizableInstr recogInstr(tables, insn, uid);
269 recogInstr.emitInstructionSpecifier(tables);
271 if (recogInstr.shouldBeEmitted())
272 recogInstr.emitDecodePath(tables);
275 InstructionContext RecognizableInstr::insnContext() const {
276 InstructionContext insnContext;
278 if (HasVEX_4VPrefix || HasVEXPrefix) {
279 if (HasOpSizePrefix && HasVEX_LPrefix)
280 insnContext = IC_VEX_L_OPSIZE;
281 else if (HasOpSizePrefix && HasVEX_WPrefix)
282 insnContext = IC_VEX_W_OPSIZE;
283 else if (HasOpSizePrefix)
284 insnContext = IC_VEX_OPSIZE;
285 else if (HasVEX_LPrefix && Prefix == X86Local::XS)
286 insnContext = IC_VEX_L_XS;
287 else if (HasVEX_LPrefix && Prefix == X86Local::XD)
288 insnContext = IC_VEX_L_XD;
289 else if (HasVEX_WPrefix && Prefix == X86Local::XS)
290 insnContext = IC_VEX_W_XS;
291 else if (HasVEX_WPrefix && Prefix == X86Local::XD)
292 insnContext = IC_VEX_W_XD;
293 else if (HasVEX_WPrefix)
294 insnContext = IC_VEX_W;
295 else if (HasVEX_LPrefix)
296 insnContext = IC_VEX_L;
297 else if (Prefix == X86Local::XD)
298 insnContext = IC_VEX_XD;
299 else if (Prefix == X86Local::XS)
300 insnContext = IC_VEX_XS;
302 insnContext = IC_VEX;
303 } else if (Is64Bit || HasREX_WPrefix) {
304 if (HasREX_WPrefix && HasOpSizePrefix)
305 insnContext = IC_64BIT_REXW_OPSIZE;
306 else if (HasOpSizePrefix)
307 insnContext = IC_64BIT_OPSIZE;
308 else if (HasREX_WPrefix && Prefix == X86Local::XS)
309 insnContext = IC_64BIT_REXW_XS;
310 else if (HasREX_WPrefix && Prefix == X86Local::XD)
311 insnContext = IC_64BIT_REXW_XD;
312 else if (Prefix == X86Local::XD)
313 insnContext = IC_64BIT_XD;
314 else if (Prefix == X86Local::XS)
315 insnContext = IC_64BIT_XS;
316 else if (HasREX_WPrefix)
317 insnContext = IC_64BIT_REXW;
319 insnContext = IC_64BIT;
322 insnContext = IC_OPSIZE;
323 else if (Prefix == X86Local::XD)
325 else if (Prefix == X86Local::XS)
334 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
339 // Filter out intrinsics
341 if (!Rec->isSubClassOf("X86Inst"))
342 return FILTER_STRONG;
344 if (Form == X86Local::Pseudo ||
346 return FILTER_STRONG;
348 if (Form == X86Local::MRMInitReg)
349 return FILTER_STRONG;
352 // TEMPORARY pending bug fixes
354 if (Name.find("VMOVDQU") != Name.npos ||
355 Name.find("VMOVDQA") != Name.npos ||
356 Name.find("VROUND") != Name.npos)
357 return FILTER_STRONG;
359 // Filter out artificial instructions
361 if (Name.find("TAILJMP") != Name.npos ||
362 Name.find("_Int") != Name.npos ||
363 Name.find("_int") != Name.npos ||
364 Name.find("Int_") != Name.npos ||
365 Name.find("_NOREX") != Name.npos ||
366 Name.find("_TC") != Name.npos ||
367 Name.find("EH_RETURN") != Name.npos ||
368 Name.find("V_SET") != Name.npos ||
369 Name.find("LOCK_") != Name.npos ||
370 Name.find("WIN") != Name.npos ||
371 Name.find("_AVX") != Name.npos ||
372 Name.find("2SDL") != Name.npos)
373 return FILTER_STRONG;
375 // Filter out instructions with segment override prefixes.
376 // They're too messy to handle now and we'll special case them if needed.
379 return FILTER_STRONG;
381 // Filter out instructions that can't be printed.
383 if (AsmString.size() == 0)
384 return FILTER_STRONG;
386 // Filter out instructions with subreg operands.
388 if (AsmString.find("subreg") != AsmString.npos)
389 return FILTER_STRONG;
396 // Filter out instructions with a LOCK prefix;
397 // prefer forms that do not have the prefix
401 // Filter out alternate forms of AVX instructions
402 if (Name.find("_alt") != Name.npos ||
403 Name.find("XrYr") != Name.npos ||
404 Name.find("r64r") != Name.npos ||
405 Name.find("_64mr") != Name.npos ||
406 Name.find("Xrr") != Name.npos ||
407 Name.find("rr64") != Name.npos)
410 if (Name == "VMASKMOVDQU64" ||
411 Name == "VEXTRACTPSrr64" ||
412 Name == "VMOVQd64rr" ||
413 Name == "VMOVQs64rr")
418 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
420 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
423 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
425 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
427 if (Name.find("Fs") != Name.npos)
429 if (Name == "MOVLPDrr" ||
430 Name == "MOVLPSrr" ||
436 Name == "MOVSX16rm8" ||
437 Name == "MOVSX16rr8" ||
438 Name == "MOVZX16rm8" ||
439 Name == "MOVZX16rr8" ||
440 Name == "PUSH32i16" ||
441 Name == "PUSH64i16" ||
442 Name == "MOVPQI2QImr" ||
443 Name == "VMOVPQI2QImr" ||
448 Name == "MMX_MOVD64rrv164" ||
449 Name == "CRC32m16" ||
450 Name == "MOV64ri64i32" ||
454 if (HasFROperands && Name.find("MOV") != Name.npos &&
455 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
456 (Name.find("to") != Name.npos)))
459 return FILTER_NORMAL;
462 bool RecognizableInstr::hasFROperands() const {
463 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
464 unsigned numOperands = OperandList.size();
466 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
467 const std::string &recName = OperandList[operandIndex].Rec->getName();
469 if (recName.find("FR") != recName.npos)
475 bool RecognizableInstr::has256BitOperands() const {
476 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
477 unsigned numOperands = OperandList.size();
479 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
480 const std::string &recName = OperandList[operandIndex].Rec->getName();
482 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
489 void RecognizableInstr::handleOperand(
491 unsigned &operandIndex,
492 unsigned &physicalOperandIndex,
493 unsigned &numPhysicalOperands,
494 unsigned *operandMapping,
495 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
497 if (physicalOperandIndex >= numPhysicalOperands)
500 assert(physicalOperandIndex < numPhysicalOperands);
503 while (operandMapping[operandIndex] != operandIndex) {
504 Spec->operands[operandIndex].encoding = ENCODING_DUP;
505 Spec->operands[operandIndex].type =
506 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
510 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
512 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
514 Spec->operands[operandIndex].type = typeFromString(typeName,
520 ++physicalOperandIndex;
523 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
526 if (!Rec->isSubClassOf("X86Inst"))
531 Spec->filtered = true;
534 ShouldBeEmitted = false;
540 Spec->insnContext = insnContext();
542 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
544 unsigned operandIndex;
545 unsigned numOperands = OperandList.size();
546 unsigned numPhysicalOperands = 0;
548 // operandMapping maps from operands in OperandList to their originals.
549 // If operandMapping[i] != i, then the entry is a duplicate.
550 unsigned operandMapping[X86_MAX_OPERANDS];
552 bool hasFROperands = false;
554 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
556 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
557 if (OperandList[operandIndex].Constraints.size()) {
558 const CGIOperandList::ConstraintInfo &Constraint =
559 OperandList[operandIndex].Constraints[0];
560 if (Constraint.isTied()) {
561 operandMapping[operandIndex] = Constraint.getTiedOperand();
563 ++numPhysicalOperands;
564 operandMapping[operandIndex] = operandIndex;
567 ++numPhysicalOperands;
568 operandMapping[operandIndex] = operandIndex;
571 const std::string &recName = OperandList[operandIndex].Rec->getName();
573 if (recName.find("FR") != recName.npos)
574 hasFROperands = true;
577 if (hasFROperands && Name.find("MOV") != Name.npos &&
578 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
579 (Name.find("to") != Name.npos)))
580 ShouldBeEmitted = false;
582 if (!ShouldBeEmitted)
585 #define HANDLE_OPERAND(class) \
586 handleOperand(false, \
588 physicalOperandIndex, \
589 numPhysicalOperands, \
591 class##EncodingFromString);
593 #define HANDLE_OPTIONAL(class) \
594 handleOperand(true, \
596 physicalOperandIndex, \
597 numPhysicalOperands, \
599 class##EncodingFromString);
601 // operandIndex should always be < numOperands
603 // physicalOperandIndex should always be < numPhysicalOperands
604 unsigned physicalOperandIndex = 0;
607 case X86Local::RawFrm:
608 // Operand 1 (optional) is an address or immediate.
609 // Operand 2 (optional) is an immediate.
610 assert(numPhysicalOperands <= 2 &&
611 "Unexpected number of operands for RawFrm");
612 HANDLE_OPTIONAL(relocation)
613 HANDLE_OPTIONAL(immediate)
615 case X86Local::AddRegFrm:
616 // Operand 1 is added to the opcode.
617 // Operand 2 (optional) is an address.
618 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
619 "Unexpected number of operands for AddRegFrm");
620 HANDLE_OPERAND(opcodeModifier)
621 HANDLE_OPTIONAL(relocation)
623 case X86Local::MRMDestReg:
624 // Operand 1 is a register operand in the R/M field.
625 // Operand 2 is a register operand in the Reg/Opcode field.
626 // - In AVX, there is a register operand in the VEX.vvvv field here -
627 // Operand 3 (optional) is an immediate.
629 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
630 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
632 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
633 "Unexpected number of operands for MRMDestRegFrm");
635 HANDLE_OPERAND(rmRegister)
638 // FIXME: In AVX, the register below becomes the one encoded
639 // in ModRMVEX and the one above the one in the VEX.VVVV field
640 HANDLE_OPERAND(vvvvRegister)
642 HANDLE_OPERAND(roRegister)
643 HANDLE_OPTIONAL(immediate)
645 case X86Local::MRMDestMem:
646 // Operand 1 is a memory operand (possibly SIB-extended)
647 // Operand 2 is a register operand in the Reg/Opcode field.
648 // - In AVX, there is a register operand in the VEX.vvvv field here -
649 // Operand 3 (optional) is an immediate.
651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
652 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
655 "Unexpected number of operands for MRMDestMemFrm");
656 HANDLE_OPERAND(memory)
659 // FIXME: In AVX, the register below becomes the one encoded
660 // in ModRMVEX and the one above the one in the VEX.VVVV field
661 HANDLE_OPERAND(vvvvRegister)
663 HANDLE_OPERAND(roRegister)
664 HANDLE_OPTIONAL(immediate)
666 case X86Local::MRMSrcReg:
667 // Operand 1 is a register operand in the Reg/Opcode field.
668 // Operand 2 is a register operand in the R/M field.
669 // - In AVX, there is a register operand in the VEX.vvvv field here -
670 // Operand 3 (optional) is an immediate.
673 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
674 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
676 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
677 "Unexpected number of operands for MRMSrcRegFrm");
679 HANDLE_OPERAND(roRegister)
682 // FIXME: In AVX, the register below becomes the one encoded
683 // in ModRMVEX and the one above the one in the VEX.VVVV field
684 HANDLE_OPERAND(vvvvRegister)
686 HANDLE_OPERAND(rmRegister)
687 HANDLE_OPTIONAL(immediate)
689 case X86Local::MRMSrcMem:
690 // Operand 1 is a register operand in the Reg/Opcode field.
691 // Operand 2 is a memory operand (possibly SIB-extended)
692 // - In AVX, there is a register operand in the VEX.vvvv field here -
693 // Operand 3 (optional) is an immediate.
696 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
697 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
699 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
700 "Unexpected number of operands for MRMSrcMemFrm");
702 HANDLE_OPERAND(roRegister)
705 // FIXME: In AVX, the register below becomes the one encoded
706 // in ModRMVEX and the one above the one in the VEX.VVVV field
707 HANDLE_OPERAND(vvvvRegister)
709 HANDLE_OPERAND(memory)
710 HANDLE_OPTIONAL(immediate)
712 case X86Local::MRM0r:
713 case X86Local::MRM1r:
714 case X86Local::MRM2r:
715 case X86Local::MRM3r:
716 case X86Local::MRM4r:
717 case X86Local::MRM5r:
718 case X86Local::MRM6r:
719 case X86Local::MRM7r:
720 // Operand 1 is a register operand in the R/M field.
721 // Operand 2 (optional) is an immediate or relocation.
723 assert(numPhysicalOperands <= 3 &&
724 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
726 assert(numPhysicalOperands <= 2 &&
727 "Unexpected number of operands for MRMnRFrm");
729 HANDLE_OPERAND(vvvvRegister);
730 HANDLE_OPTIONAL(rmRegister)
731 HANDLE_OPTIONAL(relocation)
733 case X86Local::MRM0m:
734 case X86Local::MRM1m:
735 case X86Local::MRM2m:
736 case X86Local::MRM3m:
737 case X86Local::MRM4m:
738 case X86Local::MRM5m:
739 case X86Local::MRM6m:
740 case X86Local::MRM7m:
741 // Operand 1 is a memory operand (possibly SIB-extended)
742 // Operand 2 (optional) is an immediate or relocation.
743 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
744 "Unexpected number of operands for MRMnMFrm");
745 HANDLE_OPERAND(memory)
746 HANDLE_OPTIONAL(relocation)
748 case X86Local::RawFrmImm8:
749 // operand 1 is a 16-bit immediate
750 // operand 2 is an 8-bit immediate
751 assert(numPhysicalOperands == 2 &&
752 "Unexpected number of operands for X86Local::RawFrmImm8");
753 HANDLE_OPERAND(immediate)
754 HANDLE_OPERAND(immediate)
756 case X86Local::RawFrmImm16:
757 // operand 1 is a 16-bit immediate
758 // operand 2 is a 16-bit immediate
759 HANDLE_OPERAND(immediate)
760 HANDLE_OPERAND(immediate)
762 case X86Local::MRMInitReg:
767 #undef HANDLE_OPERAND
768 #undef HANDLE_OPTIONAL
771 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
772 // Special cases where the LLVM tables are not complete
774 #define MAP(from, to) \
775 case X86Local::MRM_##from: \
776 filter = new ExactFilter(0x##from); \
779 OpcodeType opcodeType = (OpcodeType)-1;
781 ModRMFilter* filter = NULL;
782 uint8_t opcodeToSet = 0;
785 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
789 opcodeType = TWOBYTE;
793 if (needsModRMForDecode(Form))
794 filter = new ModFilter(isRegFormat(Form));
796 filter = new DumbFilter();
798 #define EXTENSION_TABLE(n) case 0x##n:
799 TWO_BYTE_EXTENSION_TABLES
800 #undef EXTENSION_TABLE
803 llvm_unreachable("Unhandled two-byte extended opcode");
804 case X86Local::MRM0r:
805 case X86Local::MRM1r:
806 case X86Local::MRM2r:
807 case X86Local::MRM3r:
808 case X86Local::MRM4r:
809 case X86Local::MRM5r:
810 case X86Local::MRM6r:
811 case X86Local::MRM7r:
812 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
814 case X86Local::MRM0m:
815 case X86Local::MRM1m:
816 case X86Local::MRM2m:
817 case X86Local::MRM3m:
818 case X86Local::MRM4m:
819 case X86Local::MRM5m:
820 case X86Local::MRM6m:
821 case X86Local::MRM7m:
822 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
828 opcodeToSet = Opcode;
832 opcodeType = THREEBYTE_38;
833 if (needsModRMForDecode(Form))
834 filter = new ModFilter(isRegFormat(Form));
836 filter = new DumbFilter();
837 opcodeToSet = Opcode;
840 opcodeType = THREEBYTE_3A;
841 if (needsModRMForDecode(Form))
842 filter = new ModFilter(isRegFormat(Form));
844 filter = new DumbFilter();
845 opcodeToSet = Opcode;
848 opcodeType = THREEBYTE_A6;
849 if (needsModRMForDecode(Form))
850 filter = new ModFilter(isRegFormat(Form));
852 filter = new DumbFilter();
853 opcodeToSet = Opcode;
856 opcodeType = THREEBYTE_A7;
857 if (needsModRMForDecode(Form))
858 filter = new ModFilter(isRegFormat(Form));
860 filter = new DumbFilter();
861 opcodeToSet = Opcode;
871 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
872 opcodeType = ONEBYTE;
873 if (Form == X86Local::AddRegFrm) {
874 Spec->modifierType = MODIFIER_MODRM;
875 Spec->modifierBase = Opcode;
876 filter = new AddRegEscapeFilter(Opcode);
878 filter = new EscapeFilter(true, Opcode);
880 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
883 opcodeType = ONEBYTE;
885 #define EXTENSION_TABLE(n) case 0x##n:
886 ONE_BYTE_EXTENSION_TABLES
887 #undef EXTENSION_TABLE
890 llvm_unreachable("Fell through the cracks of a single-byte "
892 case X86Local::MRM0r:
893 case X86Local::MRM1r:
894 case X86Local::MRM2r:
895 case X86Local::MRM3r:
896 case X86Local::MRM4r:
897 case X86Local::MRM5r:
898 case X86Local::MRM6r:
899 case X86Local::MRM7r:
900 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
902 case X86Local::MRM0m:
903 case X86Local::MRM1m:
904 case X86Local::MRM2m:
905 case X86Local::MRM3m:
906 case X86Local::MRM4m:
907 case X86Local::MRM5m:
908 case X86Local::MRM6m:
909 case X86Local::MRM7m:
910 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
923 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
926 if (needsModRMForDecode(Form))
927 filter = new ModFilter(isRegFormat(Form));
929 filter = new DumbFilter();
932 opcodeToSet = Opcode;
935 assert(opcodeType != (OpcodeType)-1 &&
936 "Opcode type not set");
937 assert(filter && "Filter not set");
939 if (Form == X86Local::AddRegFrm) {
940 if(Spec->modifierType != MODIFIER_MODRM) {
941 assert(opcodeToSet < 0xf9 &&
942 "Not enough room for all ADDREG_FRM operands");
944 uint8_t currentOpcode;
946 for (currentOpcode = opcodeToSet;
947 currentOpcode < opcodeToSet + 8;
949 tables.setTableFields(opcodeType,
955 Spec->modifierType = MODIFIER_OPCODE;
956 Spec->modifierBase = opcodeToSet;
958 // modifierBase was set where MODIFIER_MODRM was set
959 tables.setTableFields(opcodeType,
966 tables.setTableFields(opcodeType,
972 Spec->modifierType = MODIFIER_NONE;
973 Spec->modifierBase = opcodeToSet;
981 #define TYPE(str, type) if (s == str) return type;
982 OperandType RecognizableInstr::typeFromString(const std::string &s,
985 bool hasOpSizePrefix) {
987 // For SSE instructions, we ignore the OpSize prefix and force operand
989 TYPE("GR16", TYPE_R16)
990 TYPE("GR32", TYPE_R32)
991 TYPE("GR64", TYPE_R64)
994 // For instructions with a REX_W prefix, a declared 32-bit register encoding
996 TYPE("GR32", TYPE_R32)
998 if(!hasOpSizePrefix) {
999 // For instructions without an OpSize prefix, a declared 16-bit register or
1000 // immediate encoding is special.
1001 TYPE("GR16", TYPE_R16)
1002 TYPE("i16imm", TYPE_IMM16)
1004 TYPE("i16mem", TYPE_Mv)
1005 TYPE("i16imm", TYPE_IMMv)
1006 TYPE("i16i8imm", TYPE_IMMv)
1007 TYPE("GR16", TYPE_Rv)
1008 TYPE("i32mem", TYPE_Mv)
1009 TYPE("i32imm", TYPE_IMMv)
1010 TYPE("i32i8imm", TYPE_IMM32)
1011 TYPE("u32u8imm", TYPE_IMM32)
1012 TYPE("GR32", TYPE_Rv)
1013 TYPE("i64mem", TYPE_Mv)
1014 TYPE("i64i32imm", TYPE_IMM64)
1015 TYPE("i64i8imm", TYPE_IMM64)
1016 TYPE("GR64", TYPE_R64)
1017 TYPE("i8mem", TYPE_M8)
1018 TYPE("i8imm", TYPE_IMM8)
1019 TYPE("GR8", TYPE_R8)
1020 TYPE("VR128", TYPE_XMM128)
1021 TYPE("f128mem", TYPE_M128)
1022 TYPE("f256mem", TYPE_M256)
1023 TYPE("FR64", TYPE_XMM64)
1024 TYPE("f64mem", TYPE_M64FP)
1025 TYPE("sdmem", TYPE_M64FP)
1026 TYPE("FR32", TYPE_XMM32)
1027 TYPE("f32mem", TYPE_M32FP)
1028 TYPE("ssmem", TYPE_M32FP)
1029 TYPE("RST", TYPE_ST)
1030 TYPE("i128mem", TYPE_M128)
1031 TYPE("i256mem", TYPE_M256)
1032 TYPE("i64i32imm_pcrel", TYPE_REL64)
1033 TYPE("i16imm_pcrel", TYPE_REL16)
1034 TYPE("i32imm_pcrel", TYPE_REL32)
1035 TYPE("SSECC", TYPE_IMM3)
1036 TYPE("brtarget", TYPE_RELv)
1037 TYPE("uncondbrtarget", TYPE_RELv)
1038 TYPE("brtarget8", TYPE_REL8)
1039 TYPE("f80mem", TYPE_M80FP)
1040 TYPE("lea32mem", TYPE_LEA)
1041 TYPE("lea64_32mem", TYPE_LEA)
1042 TYPE("lea64mem", TYPE_LEA)
1043 TYPE("VR64", TYPE_MM64)
1044 TYPE("i64imm", TYPE_IMMv)
1045 TYPE("opaque32mem", TYPE_M1616)
1046 TYPE("opaque48mem", TYPE_M1632)
1047 TYPE("opaque80mem", TYPE_M1664)
1048 TYPE("opaque512mem", TYPE_M512)
1049 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1050 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1051 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1052 TYPE("offset8", TYPE_MOFFS8)
1053 TYPE("offset16", TYPE_MOFFS16)
1054 TYPE("offset32", TYPE_MOFFS32)
1055 TYPE("offset64", TYPE_MOFFS64)
1056 TYPE("VR256", TYPE_XMM256)
1057 errs() << "Unhandled type string " << s << "\n";
1058 llvm_unreachable("Unhandled type string");
1062 #define ENCODING(str, encoding) if (s == str) return encoding;
1063 OperandEncoding RecognizableInstr::immediateEncodingFromString
1064 (const std::string &s,
1065 bool hasOpSizePrefix) {
1066 if(!hasOpSizePrefix) {
1067 // For instructions without an OpSize prefix, a declared 16-bit register or
1068 // immediate encoding is special.
1069 ENCODING("i16imm", ENCODING_IW)
1071 ENCODING("i32i8imm", ENCODING_IB)
1072 ENCODING("u32u8imm", ENCODING_IB)
1073 ENCODING("SSECC", ENCODING_IB)
1074 ENCODING("i16imm", ENCODING_Iv)
1075 ENCODING("i16i8imm", ENCODING_IB)
1076 ENCODING("i32imm", ENCODING_Iv)
1077 ENCODING("i64i32imm", ENCODING_ID)
1078 ENCODING("i64i8imm", ENCODING_IB)
1079 ENCODING("i8imm", ENCODING_IB)
1080 // This is not a typo. Instructions like BLENDVPD put
1081 // register IDs in 8-bit immediates nowadays.
1082 ENCODING("VR256", ENCODING_IB)
1083 ENCODING("VR128", ENCODING_IB)
1084 errs() << "Unhandled immediate encoding " << s << "\n";
1085 llvm_unreachable("Unhandled immediate encoding");
1088 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1089 (const std::string &s,
1090 bool hasOpSizePrefix) {
1091 ENCODING("GR16", ENCODING_RM)
1092 ENCODING("GR32", ENCODING_RM)
1093 ENCODING("GR64", ENCODING_RM)
1094 ENCODING("GR8", ENCODING_RM)
1095 ENCODING("VR128", ENCODING_RM)
1096 ENCODING("FR64", ENCODING_RM)
1097 ENCODING("FR32", ENCODING_RM)
1098 ENCODING("VR64", ENCODING_RM)
1099 ENCODING("VR256", ENCODING_RM)
1100 errs() << "Unhandled R/M register encoding " << s << "\n";
1101 llvm_unreachable("Unhandled R/M register encoding");
1104 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1105 (const std::string &s,
1106 bool hasOpSizePrefix) {
1107 ENCODING("GR16", ENCODING_REG)
1108 ENCODING("GR32", ENCODING_REG)
1109 ENCODING("GR64", ENCODING_REG)
1110 ENCODING("GR8", ENCODING_REG)
1111 ENCODING("VR128", ENCODING_REG)
1112 ENCODING("FR64", ENCODING_REG)
1113 ENCODING("FR32", ENCODING_REG)
1114 ENCODING("VR64", ENCODING_REG)
1115 ENCODING("SEGMENT_REG", ENCODING_REG)
1116 ENCODING("DEBUG_REG", ENCODING_REG)
1117 ENCODING("CONTROL_REG", ENCODING_REG)
1118 ENCODING("VR256", ENCODING_REG)
1119 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1120 llvm_unreachable("Unhandled reg/opcode register encoding");
1123 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1124 (const std::string &s,
1125 bool hasOpSizePrefix) {
1126 ENCODING("FR32", ENCODING_VVVV)
1127 ENCODING("FR64", ENCODING_VVVV)
1128 ENCODING("VR128", ENCODING_VVVV)
1129 ENCODING("VR256", ENCODING_VVVV)
1130 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1131 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1134 OperandEncoding RecognizableInstr::memoryEncodingFromString
1135 (const std::string &s,
1136 bool hasOpSizePrefix) {
1137 ENCODING("i16mem", ENCODING_RM)
1138 ENCODING("i32mem", ENCODING_RM)
1139 ENCODING("i64mem", ENCODING_RM)
1140 ENCODING("i8mem", ENCODING_RM)
1141 ENCODING("ssmem", ENCODING_RM)
1142 ENCODING("sdmem", ENCODING_RM)
1143 ENCODING("f128mem", ENCODING_RM)
1144 ENCODING("f256mem", ENCODING_RM)
1145 ENCODING("f64mem", ENCODING_RM)
1146 ENCODING("f32mem", ENCODING_RM)
1147 ENCODING("i128mem", ENCODING_RM)
1148 ENCODING("i256mem", ENCODING_RM)
1149 ENCODING("f80mem", ENCODING_RM)
1150 ENCODING("lea32mem", ENCODING_RM)
1151 ENCODING("lea64_32mem", ENCODING_RM)
1152 ENCODING("lea64mem", ENCODING_RM)
1153 ENCODING("opaque32mem", ENCODING_RM)
1154 ENCODING("opaque48mem", ENCODING_RM)
1155 ENCODING("opaque80mem", ENCODING_RM)
1156 ENCODING("opaque512mem", ENCODING_RM)
1157 errs() << "Unhandled memory encoding " << s << "\n";
1158 llvm_unreachable("Unhandled memory encoding");
1161 OperandEncoding RecognizableInstr::relocationEncodingFromString
1162 (const std::string &s,
1163 bool hasOpSizePrefix) {
1164 if(!hasOpSizePrefix) {
1165 // For instructions without an OpSize prefix, a declared 16-bit register or
1166 // immediate encoding is special.
1167 ENCODING("i16imm", ENCODING_IW)
1169 ENCODING("i16imm", ENCODING_Iv)
1170 ENCODING("i16i8imm", ENCODING_IB)
1171 ENCODING("i32imm", ENCODING_Iv)
1172 ENCODING("i32i8imm", ENCODING_IB)
1173 ENCODING("i64i32imm", ENCODING_ID)
1174 ENCODING("i64i8imm", ENCODING_IB)
1175 ENCODING("i8imm", ENCODING_IB)
1176 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1177 ENCODING("i16imm_pcrel", ENCODING_IW)
1178 ENCODING("i32imm_pcrel", ENCODING_ID)
1179 ENCODING("brtarget", ENCODING_Iv)
1180 ENCODING("brtarget8", ENCODING_IB)
1181 ENCODING("i64imm", ENCODING_IO)
1182 ENCODING("offset8", ENCODING_Ia)
1183 ENCODING("offset16", ENCODING_Ia)
1184 ENCODING("offset32", ENCODING_Ia)
1185 ENCODING("offset64", ENCODING_Ia)
1186 errs() << "Unhandled relocation encoding " << s << "\n";
1187 llvm_unreachable("Unhandled relocation encoding");
1190 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1191 (const std::string &s,
1192 bool hasOpSizePrefix) {
1193 ENCODING("RST", ENCODING_I)
1194 ENCODING("GR32", ENCODING_Rv)
1195 ENCODING("GR64", ENCODING_RO)
1196 ENCODING("GR16", ENCODING_Rv)
1197 ENCODING("GR8", ENCODING_RB)
1198 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1199 llvm_unreachable("Unhandled opcode modifier encoding");