1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return inheritsFrom(child, IC_VEX_L_W) ||
85 inheritsFrom(child, IC_VEX_W) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
88 return inheritsFrom(child, IC_VEX_L_W_XS) ||
89 inheritsFrom(child, IC_VEX_W_XS) ||
90 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
92 return inheritsFrom(child, IC_VEX_L_W_XD) ||
93 inheritsFrom(child, IC_VEX_W_XD) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
96 return inheritsFrom(child, IC_VEX_L_W_OPSIZE) ||
97 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
98 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
102 case IC_VEX_W_OPSIZE:
107 case IC_VEX_L_OPSIZE:
112 case IC_VEX_L_W_OPSIZE:
115 return inheritsFrom(child, IC_EVEX_W) ||
116 inheritsFrom(child, IC_EVEX_L_W);
118 return inheritsFrom(child, IC_EVEX_W_XS) ||
119 inheritsFrom(child, IC_EVEX_L_W_XS);
121 return inheritsFrom(child, IC_EVEX_W_XD) ||
122 inheritsFrom(child, IC_EVEX_L_W_XD);
124 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
125 inheritsFrom(child, IC_EVEX_W_OPSIZE);
129 case IC_EVEX_W_OPSIZE:
134 case IC_EVEX_L_OPSIZE:
139 case IC_EVEX_L_W_OPSIZE:
144 case IC_EVEX_L2_OPSIZE:
147 case IC_EVEX_L2_W_XS:
148 case IC_EVEX_L2_W_XD:
149 case IC_EVEX_L2_W_OPSIZE:
152 return inheritsFrom(child, IC_EVEX_W_K) ||
153 inheritsFrom(child, IC_EVEX_L_W_K);
155 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
156 inheritsFrom(child, IC_EVEX_L_W_XS_K);
158 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
159 inheritsFrom(child, IC_EVEX_L_W_XD_K);
160 case IC_EVEX_OPSIZE_K:
161 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
162 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
166 case IC_EVEX_W_OPSIZE_K:
171 case IC_EVEX_L_OPSIZE_K:
174 case IC_EVEX_L_W_XS_K:
175 case IC_EVEX_L_W_XD_K:
176 case IC_EVEX_L_W_OPSIZE_K:
180 case IC_EVEX_L2_XS_K:
181 case IC_EVEX_L2_XD_K:
182 case IC_EVEX_L2_OPSIZE_K:
183 case IC_EVEX_L2_OPSIZE_B:
186 case IC_EVEX_L2_W_XS_K:
187 case IC_EVEX_L2_W_XD_K:
188 case IC_EVEX_L2_W_OPSIZE_K:
189 case IC_EVEX_L2_W_OPSIZE_B:
192 llvm_unreachable("Unknown instruction class");
196 /// outranks - Indicates whether, if an instruction has two different applicable
197 /// classes, which class should be preferred when performing decode. This
198 /// imposes a total ordering (ties are resolved toward "lower")
200 /// @param upper - The class that may be preferable
201 /// @param lower - The class that may be less preferable
202 /// @return - True if upper is to be preferred, false otherwise.
203 static inline bool outranks(InstructionContext upper,
204 InstructionContext lower) {
205 assert(upper < IC_max);
206 assert(lower < IC_max);
208 #define ENUM_ENTRY(n, r, d) r,
209 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
210 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
211 static int ranks[IC_max] = {
215 #undef ENUM_ENTRY_K_B
217 return (ranks[upper] > ranks[lower]);
220 /// stringForContext - Returns a string containing the name of a particular
221 /// InstructionContext, usually for diagnostic purposes.
223 /// @param insnContext - The instruction class to transform to a string.
224 /// @return - A statically-allocated string constant that contains the
225 /// name of the instruction class.
226 static inline const char* stringForContext(InstructionContext insnContext) {
227 switch (insnContext) {
229 llvm_unreachable("Unhandled instruction class");
230 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
231 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
232 ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
235 #undef ENUM_ENTRY_K_B
239 /// stringForOperandType - Like stringForContext, but for OperandTypes.
240 static inline const char* stringForOperandType(OperandType type) {
243 llvm_unreachable("Unhandled type");
244 #define ENUM_ENTRY(i, d) case i: return #i;
250 /// stringForOperandEncoding - like stringForContext, but for
251 /// OperandEncodings.
252 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
255 llvm_unreachable("Unhandled encoding");
256 #define ENUM_ENTRY(i, d) case i: return #i;
262 void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id,
263 bool addComma) const {
265 o.indent(i * 2) << format("0x%hx", id);
267 o.indent(i * 2) << 0;
275 o << InstructionSpecifiers[id].name;
281 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
282 /// all ModR/M decisions for instructions that are invalid for all possible
283 /// ModR/M byte values.
285 /// @param o - The output stream on which to emit the table.
286 /// @param i - The indentation level for that output stream.
287 static void emitEmptyTable(raw_ostream &o, unsigned &i) {
288 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
291 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
292 /// be compacted by eliminating redundant information.
294 /// @param decision - The decision to be compacted.
295 /// @return - The compactest available representation for the decision.
296 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
297 bool satisfiesOneEntry = true;
298 bool satisfiesSplitRM = true;
299 bool satisfiesSplitReg = true;
300 bool satisfiesSplitMisc = true;
302 for (unsigned index = 0; index < 256; ++index) {
303 if (decision.instructionIDs[index] != decision.instructionIDs[0])
304 satisfiesOneEntry = false;
306 if (((index & 0xc0) == 0xc0) &&
307 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
308 satisfiesSplitRM = false;
310 if (((index & 0xc0) != 0xc0) &&
311 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
312 satisfiesSplitRM = false;
314 if (((index & 0xc0) == 0xc0) &&
315 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
316 satisfiesSplitReg = false;
318 if (((index & 0xc0) != 0xc0) &&
319 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
320 satisfiesSplitMisc = false;
323 if (satisfiesOneEntry)
324 return MODRM_ONEENTRY;
326 if (satisfiesSplitRM)
327 return MODRM_SPLITRM;
329 if (satisfiesSplitReg && satisfiesSplitMisc)
330 return MODRM_SPLITREG;
332 if (satisfiesSplitMisc)
333 return MODRM_SPLITMISC;
338 /// stringForDecisionType - Returns a statically-allocated string corresponding
339 /// to a particular decision type.
341 /// @param dt - The decision type.
342 /// @return - A pointer to the statically-allocated string (e.g.,
343 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
344 static const char* stringForDecisionType(ModRMDecisionType dt) {
345 #define ENUM_ENTRY(n) case n: return #n;
348 llvm_unreachable("Unknown decision type");
354 /// stringForModifierType - Returns a statically-allocated string corresponding
355 /// to an opcode modifier type.
357 /// @param mt - The modifier type.
358 /// @return - A pointer to the statically-allocated string (e.g.,
359 /// "MODIFIER_NONE" for MODIFIER_NONE).
360 static const char* stringForModifierType(ModifierType mt) {
361 #define ENUM_ENTRY(n) case n: return #n;
364 llvm_unreachable("Unknown modifier type");
370 DisassemblerTables::DisassemblerTables() {
373 for (i = 0; i < array_lengthof(Tables); i++) {
374 Tables[i] = new ContextDecision;
375 memset(Tables[i], 0, sizeof(ContextDecision));
378 HasConflicts = false;
381 DisassemblerTables::~DisassemblerTables() {
384 for (i = 0; i < array_lengthof(Tables); i++)
388 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
389 unsigned &i1, unsigned &i2,
390 ModRMDecision &decision) const {
391 static uint32_t sTableNumber = 0;
392 static uint32_t sEntryNumber = 1;
393 ModRMDecisionType dt = getDecisionType(decision);
395 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
397 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
400 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
401 o2.indent(i2) << 0 << " /* EmptyTable */\n";
404 o2.indent(i2) << "}";
408 o1 << "/* Table" << sTableNumber << " */\n";
413 llvm_unreachable("Unknown decision type");
415 emitOneID(o1, i1, decision.instructionIDs[0], true);
418 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
419 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
422 for (unsigned index = 0; index < 64; index += 8)
423 emitOneID(o1, i1, decision.instructionIDs[index], true);
424 for (unsigned index = 0xc0; index < 256; index += 8)
425 emitOneID(o1, i1, decision.instructionIDs[index], true);
427 case MODRM_SPLITMISC:
428 for (unsigned index = 0; index < 64; index += 8)
429 emitOneID(o1, i1, decision.instructionIDs[index], true);
430 for (unsigned index = 0xc0; index < 256; ++index)
431 emitOneID(o1, i1, decision.instructionIDs[index], true);
434 for (unsigned index = 0; index < 256; ++index)
435 emitOneID(o1, i1, decision.instructionIDs[index], true);
441 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
444 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
445 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
448 o2.indent(i2) << "}";
452 llvm_unreachable("Unknown decision type");
462 case MODRM_SPLITMISC:
463 sEntryNumber += 8 + 64;
470 // We assume that the index can fit into uint16_t.
471 assert(sEntryNumber < 65536U &&
472 "Index into ModRMDecision is too large for uint16_t!");
477 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
478 unsigned &i1, unsigned &i2,
479 OpcodeDecision &decision) const {
480 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
482 o2.indent(i2) << "{" << "\n";
485 for (unsigned index = 0; index < 256; ++index) {
488 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
490 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
499 o2.indent(i2) << "}" << "\n";
501 o2.indent(i2) << "}" << "\n";
504 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
505 unsigned &i1, unsigned &i2,
506 ContextDecision &decision,
507 const char* name) const {
508 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
510 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
513 for (unsigned index = 0; index < IC_max; ++index) {
514 o2.indent(i2) << "/* ";
515 o2 << stringForContext((InstructionContext)index);
519 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
521 if (index + 1 < IC_max)
526 o2.indent(i2) << "}" << "\n";
528 o2.indent(i2) << "};" << "\n";
531 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
533 unsigned NumInstructions = InstructionSpecifiers.size();
535 o << "static const struct OperandSpecifier x86OperandSets[]["
536 << X86_MAX_OPERANDS << "] = {\n";
538 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
539 std::map<OperandListTy, unsigned> OperandSets;
541 unsigned OperandSetNum = 0;
542 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
543 OperandListTy OperandList;
545 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
547 const char *Encoding =
548 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
549 .operands[OperandIndex].encoding);
551 stringForOperandType((OperandType)InstructionSpecifiers[Index]
552 .operands[OperandIndex].type);
553 OperandList.push_back(std::make_pair(Encoding, Type));
555 unsigned &N = OperandSets[OperandList];
556 if (N != 0) continue;
560 o << " { /* " << (OperandSetNum - 1) << " */\n";
561 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
562 o << " { " << OperandList[i].first << ", "
563 << OperandList[i].second << " },\n";
569 o.indent(i * 2) << "static const struct InstructionSpecifier ";
570 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
574 for (unsigned index = 0; index < NumInstructions; ++index) {
575 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
578 o.indent(i * 2) << stringForModifierType(
579 (ModifierType)InstructionSpecifiers[index].modifierType);
582 o.indent(i * 2) << "0x";
583 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
586 OperandListTy OperandList;
587 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
589 const char *Encoding =
590 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
591 .operands[OperandIndex].encoding);
593 stringForOperandType((OperandType)InstructionSpecifiers[index]
594 .operands[OperandIndex].type);
595 OperandList.push_back(std::make_pair(Encoding, Type));
597 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
599 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
603 o.indent(i * 2) << "}";
605 if (index + 1 < NumInstructions)
612 o.indent(i * 2) << "};" << "\n";
615 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
616 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
620 for (unsigned index = 0; index < 256; ++index) {
623 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
624 o << "IC_VEX_L_W_OPSIZE";
625 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
626 o << "IC_VEX_L_OPSIZE";
627 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
629 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
631 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
632 o << "IC_VEX_W_OPSIZE";
633 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
635 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
637 else if (index & ATTR_VEXL)
639 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
641 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
642 o << "IC_VEX_OPSIZE";
643 else if ((index & ATTR_VEX) && (index & ATTR_XD))
645 else if ((index & ATTR_VEX) && (index & ATTR_XS))
647 else if (index & ATTR_VEX)
649 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
650 o << "IC_64BIT_REXW_XS";
651 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
652 o << "IC_64BIT_REXW_XD";
653 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
654 (index & ATTR_OPSIZE))
655 o << "IC_64BIT_REXW_OPSIZE";
656 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
657 o << "IC_64BIT_XD_OPSIZE";
658 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
659 o << "IC_64BIT_XS_OPSIZE";
660 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
662 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
664 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
665 o << "IC_64BIT_OPSIZE";
666 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
667 o << "IC_64BIT_ADSIZE";
668 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
669 o << "IC_64BIT_REXW";
670 else if ((index & ATTR_64BIT))
672 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
674 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
676 else if (index & ATTR_XS)
678 else if (index & ATTR_XD)
680 else if (index & ATTR_OPSIZE)
682 else if (index & ATTR_ADSIZE)
692 o << " /* " << index << " */";
698 o.indent(i * 2) << "};" << "\n";
701 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
702 unsigned &i1, unsigned &i2) const {
703 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
704 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
705 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
706 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
707 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
708 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
711 void DisassemblerTables::emit(raw_ostream &o) const {
718 raw_string_ostream o1(s1);
719 raw_string_ostream o2(s2);
721 emitInstructionInfo(o, i2);
724 emitContextTable(o, i2);
727 o << "static const InstrUID modRMTable[] = {\n";
729 emitEmptyTable(o1, i1);
731 emitContextDecisions(o1, o2, i1, i2);
742 void DisassemblerTables::setTableFields(ModRMDecision &decision,
743 const ModRMFilter &filter,
746 for (unsigned index = 0; index < 256; ++index) {
747 if (filter.accepts(index)) {
748 if (decision.instructionIDs[index] == uid)
751 if (decision.instructionIDs[index] != 0) {
752 InstructionSpecifier &newInfo =
753 InstructionSpecifiers[uid];
754 InstructionSpecifier &previousInfo =
755 InstructionSpecifiers[decision.instructionIDs[index]];
758 continue; // filtered instructions get lowest priority
760 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
761 newInfo.name == "XCHG32ar" ||
762 newInfo.name == "XCHG32ar64" ||
763 newInfo.name == "XCHG64ar"))
764 continue; // special case for XCHG*ar and NOOP
766 if (outranks(previousInfo.insnContext, newInfo.insnContext))
769 if (previousInfo.insnContext == newInfo.insnContext &&
770 !previousInfo.filtered) {
771 errs() << "Error: Primary decode conflict: ";
772 errs() << newInfo.name << " would overwrite " << previousInfo.name;
774 errs() << "ModRM " << index << "\n";
775 errs() << "Opcode " << (uint16_t)opcode << "\n";
776 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
781 decision.instructionIDs[index] = uid;
786 void DisassemblerTables::setTableFields(OpcodeType type,
787 InstructionContext insnContext,
789 const ModRMFilter &filter,
793 ContextDecision &decision = *Tables[type];
795 for (unsigned index = 0; index < IC_max; ++index) {
796 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
799 if (inheritsFrom((InstructionContext)index,
800 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
801 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],