1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits subtarget enumerations.
12 //===----------------------------------------------------------------------===//
14 #include "CodeGenTarget.h"
15 #include "CodeGenSchedule.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Format.h"
21 #include "llvm/TableGen/Error.h"
22 #include "llvm/TableGen/Record.h"
23 #include "llvm/TableGen/TableGenBackend.h"
30 #define DEBUG_TYPE "subtarget-emitter"
33 class SubtargetEmitter {
34 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
35 // The SchedClassDesc table indexes into a global write resource table, write
36 // latency table, and read advance table.
37 struct SchedClassTables {
38 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
39 std::vector<MCWriteProcResEntry> WriteProcResources;
40 std::vector<MCWriteLatencyEntry> WriteLatencies;
41 std::vector<std::string> WriterNames;
42 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
44 // Reserve an invalid entry at index 0
46 ProcSchedClasses.resize(1);
47 WriteProcResources.resize(1);
48 WriteLatencies.resize(1);
49 WriterNames.push_back("InvalidWrite");
50 ReadAdvanceEntries.resize(1);
54 struct LessWriteProcResources {
55 bool operator()(const MCWriteProcResEntry &LHS,
56 const MCWriteProcResEntry &RHS) {
57 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
61 RecordKeeper &Records;
62 CodeGenSchedModels &SchedModels;
65 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
66 unsigned FeatureKeyValues(raw_ostream &OS);
67 unsigned CPUKeyValues(raw_ostream &OS);
68 void FormItineraryStageString(const std::string &Names,
69 Record *ItinData, std::string &ItinString,
71 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
72 unsigned &NOperandCycles);
73 void FormItineraryBypassString(const std::string &Names,
75 std::string &ItinString, unsigned NOperandCycles);
76 void EmitStageAndOperandCycleData(raw_ostream &OS,
77 std::vector<std::vector<InstrItinerary> >
79 void EmitItineraries(raw_ostream &OS,
80 std::vector<std::vector<InstrItinerary> >
82 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
84 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
86 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
87 const CodeGenProcModel &ProcModel);
88 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
89 const CodeGenProcModel &ProcModel);
90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
91 const CodeGenProcModel &ProcModel);
92 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
93 SchedClassTables &SchedTables);
94 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
95 void EmitProcessorModels(raw_ostream &OS);
96 void EmitProcessorLookup(raw_ostream &OS);
97 void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS);
98 void EmitSchedModel(raw_ostream &OS);
99 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
103 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
104 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
106 void run(raw_ostream &o);
109 } // End anonymous namespace
112 // Enumeration - Emit the specified class as an enumeration.
114 void SubtargetEmitter::Enumeration(raw_ostream &OS,
115 const char *ClassName,
117 // Get all records of class and sort
118 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
119 std::sort(DefList.begin(), DefList.end(), LessRecord());
121 unsigned N = DefList.size();
125 errs() << "Too many (> 64) subtarget features!\n";
129 OS << "namespace " << Target << " {\n";
131 // Open enumeration. Use a 64-bit underlying type.
132 OS << "enum : uint64_t {\n";
135 for (unsigned i = 0; i < N;) {
137 Record *Def = DefList[i];
140 OS << " " << Def->getName();
142 // If bit flags then emit expression (1 << i)
143 if (isBits) OS << " = " << " 1ULL << " << i;
145 // Depending on 'if more in the list' emit comma
146 if (++i < N) OS << ",";
158 // FeatureKeyValues - Emit data of all the subtarget features. Used by the
161 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
162 // Gather and sort all the features
163 std::vector<Record*> FeatureList =
164 Records.getAllDerivedDefinitions("SubtargetFeature");
166 if (FeatureList.empty())
169 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
171 // Begin feature table
172 OS << "// Sorted (by key) array of values for CPU features.\n"
173 << "extern const llvm::SubtargetFeatureKV " << Target
174 << "FeatureKV[] = {\n";
177 unsigned NumFeatures = 0;
178 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
180 Record *Feature = FeatureList[i];
182 const std::string &Name = Feature->getName();
183 const std::string &CommandLineName = Feature->getValueAsString("Name");
184 const std::string &Desc = Feature->getValueAsString("Desc");
186 if (CommandLineName.empty()) continue;
188 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
190 << "\"" << CommandLineName << "\", "
191 << "\"" << Desc << "\", "
192 << Target << "::" << Name << ", ";
194 const std::vector<Record*> &ImpliesList =
195 Feature->getValueAsListOfDefs("Implies");
197 if (ImpliesList.empty()) {
200 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
201 OS << Target << "::" << ImpliesList[j]->getName();
202 if (++j < M) OS << " | ";
209 // Depending on 'if more in the list' emit comma
210 if ((i + 1) < N) OS << ",";
222 // CPUKeyValues - Emit data of all the subtarget processors. Used by command
225 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
226 // Gather and sort processor information
227 std::vector<Record*> ProcessorList =
228 Records.getAllDerivedDefinitions("Processor");
229 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
231 // Begin processor table
232 OS << "// Sorted (by key) array of values for CPU subtype.\n"
233 << "extern const llvm::SubtargetFeatureKV " << Target
234 << "SubTypeKV[] = {\n";
236 // For each processor
237 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
239 Record *Processor = ProcessorList[i];
241 const std::string &Name = Processor->getValueAsString("Name");
242 const std::vector<Record*> &FeatureList =
243 Processor->getValueAsListOfDefs("Features");
245 // Emit as { "cpu", "description", f1 | f2 | ... fn },
247 << "\"" << Name << "\", "
248 << "\"Select the " << Name << " processor\", ";
250 if (FeatureList.empty()) {
253 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
254 OS << Target << "::" << FeatureList[j]->getName();
255 if (++j < M) OS << " | ";
259 // The "0" is for the "implies" section of this data structure.
262 // Depending on 'if more in the list' emit comma
263 if (++i < N) OS << ",";
268 // End processor table
271 return ProcessorList.size();
275 // FormItineraryStageString - Compose a string containing the stage
276 // data initialization for the specified itinerary. N is the number
279 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
281 std::string &ItinString,
284 const std::vector<Record*> &StageList =
285 ItinData->getValueAsListOfDefs("Stages");
288 unsigned N = NStages = StageList.size();
289 for (unsigned i = 0; i < N;) {
291 const Record *Stage = StageList[i];
293 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
294 int Cycles = Stage->getValueAsInt("Cycles");
295 ItinString += " { " + itostr(Cycles) + ", ";
298 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
301 for (unsigned j = 0, M = UnitList.size(); j < M;) {
302 // Add name and bitwise or
303 ItinString += Name + "FU::" + UnitList[j]->getName();
304 if (++j < M) ItinString += " | ";
307 int TimeInc = Stage->getValueAsInt("TimeInc");
308 ItinString += ", " + itostr(TimeInc);
310 int Kind = Stage->getValueAsInt("Kind");
311 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
315 if (++i < N) ItinString += ", ";
320 // FormItineraryOperandCycleString - Compose a string containing the
321 // operand cycle initialization for the specified itinerary. N is the
322 // number of operands that has cycles specified.
324 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
325 std::string &ItinString, unsigned &NOperandCycles) {
326 // Get operand cycle list
327 const std::vector<int64_t> &OperandCycleList =
328 ItinData->getValueAsListOfInts("OperandCycles");
330 // For each operand cycle
331 unsigned N = NOperandCycles = OperandCycleList.size();
332 for (unsigned i = 0; i < N;) {
333 // Next operand cycle
334 const int OCycle = OperandCycleList[i];
336 ItinString += " " + itostr(OCycle);
337 if (++i < N) ItinString += ", ";
341 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
343 std::string &ItinString,
344 unsigned NOperandCycles) {
345 const std::vector<Record*> &BypassList =
346 ItinData->getValueAsListOfDefs("Bypasses");
347 unsigned N = BypassList.size();
350 ItinString += Name + "Bypass::" + BypassList[i]->getName();
351 if (++i < NOperandCycles) ItinString += ", ";
353 for (; i < NOperandCycles;) {
355 if (++i < NOperandCycles) ItinString += ", ";
360 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
361 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
362 // by CodeGenSchedClass::Index.
364 void SubtargetEmitter::
365 EmitStageAndOperandCycleData(raw_ostream &OS,
366 std::vector<std::vector<InstrItinerary> >
369 // Multiple processor models may share an itinerary record. Emit it once.
370 SmallPtrSet<Record*, 8> ItinsDefSet;
372 // Emit functional units for all the itineraries.
373 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
374 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
376 if (!ItinsDefSet.insert(PI->ItinsDef).second)
379 std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
383 const std::string &Name = PI->ItinsDef->getName();
384 OS << "\n// Functional units for \"" << Name << "\"\n"
385 << "namespace " << Name << "FU {\n";
387 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
388 OS << " const unsigned " << FUs[j]->getName()
389 << " = 1 << " << j << ";\n";
393 std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
395 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
396 << "\"\n" << "namespace " << Name << "Bypass {\n";
398 OS << " const unsigned NoBypass = 0;\n";
399 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
400 OS << " const unsigned " << BPs[j]->getName()
401 << " = 1 << " << j << ";\n";
407 // Begin stages table
408 std::string StageTable = "\nextern const llvm::InstrStage " + Target +
410 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
412 // Begin operand cycle table
413 std::string OperandCycleTable = "extern const unsigned " + Target +
414 "OperandCycles[] = {\n";
415 OperandCycleTable += " 0, // No itinerary\n";
417 // Begin pipeline bypass table
418 std::string BypassTable = "extern const unsigned " + Target +
419 "ForwardingPaths[] = {\n";
420 BypassTable += " 0, // No itinerary\n";
422 // For each Itinerary across all processors, add a unique entry to the stages,
423 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
424 // object with computed offsets to the ProcItinLists result.
425 unsigned StageCount = 1, OperandCycleCount = 1;
426 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
427 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
428 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
429 const CodeGenProcModel &ProcModel = *PI;
431 // Add process itinerary to the list.
432 ProcItinLists.resize(ProcItinLists.size()+1);
434 // If this processor defines no itineraries, then leave the itinerary list
436 std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
437 if (!ProcModel.hasItineraries())
440 const std::string &Name = ProcModel.ItinsDef->getName();
442 ItinList.resize(SchedModels.numInstrSchedClasses());
443 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
445 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
446 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
448 // Next itinerary data
449 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
451 // Get string and stage count
452 std::string ItinStageString;
453 unsigned NStages = 0;
455 FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
457 // Get string and operand cycle count
458 std::string ItinOperandCycleString;
459 unsigned NOperandCycles = 0;
460 std::string ItinBypassString;
462 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
465 FormItineraryBypassString(Name, ItinData, ItinBypassString,
469 // Check to see if stage already exists and create if it doesn't
470 unsigned FindStage = 0;
472 FindStage = ItinStageMap[ItinStageString];
473 if (FindStage == 0) {
474 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
475 StageTable += ItinStageString + ", // " + itostr(StageCount);
477 StageTable += "-" + itostr(StageCount + NStages - 1);
479 // Record Itin class number.
480 ItinStageMap[ItinStageString] = FindStage = StageCount;
481 StageCount += NStages;
485 // Check to see if operand cycle already exists and create if it doesn't
486 unsigned FindOperandCycle = 0;
487 if (NOperandCycles > 0) {
488 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
489 FindOperandCycle = ItinOperandMap[ItinOperandString];
490 if (FindOperandCycle == 0) {
491 // Emit as cycle, // index
492 OperandCycleTable += ItinOperandCycleString + ", // ";
493 std::string OperandIdxComment = itostr(OperandCycleCount);
494 if (NOperandCycles > 1)
495 OperandIdxComment += "-"
496 + itostr(OperandCycleCount + NOperandCycles - 1);
497 OperandCycleTable += OperandIdxComment + "\n";
498 // Record Itin class number.
499 ItinOperandMap[ItinOperandCycleString] =
500 FindOperandCycle = OperandCycleCount;
501 // Emit as bypass, // index
502 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
503 OperandCycleCount += NOperandCycles;
507 // Set up itinerary as location and location + stage count
508 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
509 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
511 FindOperandCycle + NOperandCycles};
513 // Inject - empty slots will be 0, 0
514 ItinList[SchedClassIdx] = Intinerary;
519 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
520 StageTable += "};\n";
522 // Closing operand cycles
523 OperandCycleTable += " 0 // End operand cycles\n";
524 OperandCycleTable += "};\n";
526 BypassTable += " 0 // End bypass tables\n";
527 BypassTable += "};\n";
531 OS << OperandCycleTable;
536 // EmitProcessorData - Generate data for processor itineraries that were
537 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
538 // Itineraries for each processor. The Itinerary lists are indexed on
539 // CodeGenSchedClass::Index.
541 void SubtargetEmitter::
542 EmitItineraries(raw_ostream &OS,
543 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
545 // Multiple processor models may share an itinerary record. Emit it once.
546 SmallPtrSet<Record*, 8> ItinsDefSet;
548 // For each processor's machine model
549 std::vector<std::vector<InstrItinerary> >::iterator
550 ProcItinListsIter = ProcItinLists.begin();
551 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
552 PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
554 Record *ItinsDef = PI->ItinsDef;
555 if (!ItinsDefSet.insert(ItinsDef).second)
558 // Get processor itinerary name
559 const std::string &Name = ItinsDef->getName();
561 // Get the itinerary list for the processor.
562 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
563 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
565 // Empty itineraries aren't referenced anywhere in the tablegen output
566 // so don't emit them.
567 if (ItinList.empty())
571 OS << "static const llvm::InstrItinerary ";
573 // Begin processor itinerary table
574 OS << Name << "[] = {\n";
576 // For each itinerary class in CodeGenSchedClass::Index order.
577 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
578 InstrItinerary &Intinerary = ItinList[j];
580 // Emit Itinerary in the form of
581 // { firstStage, lastStage, firstCycle, lastCycle } // index
583 Intinerary.NumMicroOps << ", " <<
584 Intinerary.FirstStage << ", " <<
585 Intinerary.LastStage << ", " <<
586 Intinerary.FirstOperandCycle << ", " <<
587 Intinerary.LastOperandCycle << " }" <<
588 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
590 // End processor itinerary table
591 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
596 // Emit either the value defined in the TableGen Record, or the default
597 // value defined in the C++ header. The Record is null if the processor does not
599 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
600 const char *Name, char Separator) {
602 int V = R ? R->getValueAsInt(Name) : -1;
604 OS << V << Separator << " // " << Name;
606 OS << "MCSchedModel::Default" << Name << Separator;
610 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
612 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
614 OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
615 OS << "static const llvm::MCProcResourceDesc "
616 << ProcModel.ModelName << "ProcResources" << "[] = {\n"
617 << " {DBGFIELD(\"InvalidUnit\") 0, 0, 0}" << Sep << "\n";
619 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
620 Record *PRDef = ProcModel.ProcResourceDefs[i];
622 Record *SuperDef = nullptr;
623 unsigned SuperIdx = 0;
624 unsigned NumUnits = 0;
625 int BufferSize = PRDef->getValueAsInt("BufferSize");
626 if (PRDef->isSubClassOf("ProcResGroup")) {
627 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
628 for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
630 NumUnits += (*RUI)->getValueAsInt("NumUnits");
635 if (PRDef->getValueInit("Super")->isComplete()) {
636 SuperDef = SchedModels.findProcResUnits(
637 PRDef->getValueAsDef("Super"), ProcModel);
638 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
640 NumUnits = PRDef->getValueAsInt("NumUnits");
642 // Emit the ProcResourceDesc
645 OS << " {DBGFIELD(\"" << PRDef->getName() << "\") ";
646 if (PRDef->getName().size() < 15)
647 OS.indent(15 - PRDef->getName().size());
648 OS << NumUnits << ", " << SuperIdx << ", "
649 << BufferSize << "}" << Sep << " // #" << i+1;
651 OS << ", Super=" << SuperDef->getName();
657 // Find the WriteRes Record that defines processor resources for this
659 Record *SubtargetEmitter::FindWriteResources(
660 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
662 // Check if the SchedWrite is already subtarget-specific and directly
663 // specifies a set of processor resources.
664 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
665 return SchedWrite.TheDef;
667 Record *AliasDef = nullptr;
668 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
670 const CodeGenSchedRW &AliasRW =
671 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
672 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
673 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
674 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
678 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
679 "defined for processor " + ProcModel.ModelName +
680 " Ensure only one SchedAlias exists per RW.");
681 AliasDef = AliasRW.TheDef;
683 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))
686 // Check this processor's list of write resources.
687 Record *ResDef = nullptr;
688 for (RecIter WRI = ProcModel.WriteResDefs.begin(),
689 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
690 if (!(*WRI)->isSubClassOf("WriteRes"))
692 if (AliasDef == (*WRI)->getValueAsDef("WriteType")
693 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
695 PrintFatalError((*WRI)->getLoc(), "Resources are defined for both "
696 "SchedWrite and its alias on processor " +
697 ProcModel.ModelName);
702 // TODO: If ProcModel has a base model (previous generation processor),
703 // then call FindWriteResources recursively with that model here.
705 PrintFatalError(ProcModel.ModelDef->getLoc(),
706 std::string("Processor does not define resources for ")
707 + SchedWrite.TheDef->getName());
712 /// Find the ReadAdvance record for the given SchedRead on this processor or
714 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
715 const CodeGenProcModel &ProcModel) {
716 // Check for SchedReads that directly specify a ReadAdvance.
717 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
718 return SchedRead.TheDef;
720 // Check this processor's list of aliases for SchedRead.
721 Record *AliasDef = nullptr;
722 for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
724 const CodeGenSchedRW &AliasRW =
725 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
726 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
727 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
728 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
732 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
733 "defined for processor " + ProcModel.ModelName +
734 " Ensure only one SchedAlias exists per RW.");
735 AliasDef = AliasRW.TheDef;
737 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))
740 // Check this processor's ReadAdvanceList.
741 Record *ResDef = nullptr;
742 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
743 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
744 if (!(*RAI)->isSubClassOf("ReadAdvance"))
746 if (AliasDef == (*RAI)->getValueAsDef("ReadType")
747 || SchedRead.TheDef == (*RAI)->getValueAsDef("ReadType")) {
749 PrintFatalError((*RAI)->getLoc(), "Resources are defined for both "
750 "SchedRead and its alias on processor " +
751 ProcModel.ModelName);
756 // TODO: If ProcModel has a base model (previous generation processor),
757 // then call FindReadAdvance recursively with that model here.
758 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
759 PrintFatalError(ProcModel.ModelDef->getLoc(),
760 std::string("Processor does not define resources for ")
761 + SchedRead.TheDef->getName());
766 // Expand an explicit list of processor resources into a full list of implied
767 // resource groups and super resources that cover them.
768 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
769 std::vector<int64_t> &Cycles,
770 const CodeGenProcModel &PM) {
771 // Default to 1 resource cycle.
772 Cycles.resize(PRVec.size(), 1);
773 for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
774 Record *PRDef = PRVec[i];
776 if (PRDef->isSubClassOf("ProcResGroup"))
777 SubResources = PRDef->getValueAsListOfDefs("Resources");
779 SubResources.push_back(PRDef);
780 PRDef = SchedModels.findProcResUnits(PRVec[i], PM);
781 for (Record *SubDef = PRDef;
782 SubDef->getValueInit("Super")->isComplete();) {
783 if (SubDef->isSubClassOf("ProcResGroup")) {
784 // Disallow this for simplicitly.
785 PrintFatalError(SubDef->getLoc(), "Processor resource group "
786 " cannot be a super resources.");
789 SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM);
790 PRVec.push_back(SuperDef);
791 Cycles.push_back(Cycles[i]);
795 for (RecIter PRI = PM.ProcResourceDefs.begin(),
796 PRE = PM.ProcResourceDefs.end();
798 if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup"))
800 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
801 RecIter SubI = SubResources.begin(), SubE = SubResources.end();
802 for( ; SubI != SubE; ++SubI) {
803 if (std::find(SuperResources.begin(), SuperResources.end(), *SubI)
804 == SuperResources.end()) {
809 PRVec.push_back(*PRI);
810 Cycles.push_back(Cycles[i]);
816 // Generate the SchedClass table for this processor and update global
817 // tables. Must be called for each processor in order.
818 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
819 SchedClassTables &SchedTables) {
820 SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
821 if (!ProcModel.hasInstrSchedModel())
824 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
825 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
826 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
827 DEBUG(SCI->dump(&SchedModels));
829 SCTab.resize(SCTab.size() + 1);
830 MCSchedClassDesc &SCDesc = SCTab.back();
831 // SCDesc.Name is guarded by NDEBUG
832 SCDesc.NumMicroOps = 0;
833 SCDesc.BeginGroup = false;
834 SCDesc.EndGroup = false;
835 SCDesc.WriteProcResIdx = 0;
836 SCDesc.WriteLatencyIdx = 0;
837 SCDesc.ReadAdvanceIdx = 0;
839 // A Variant SchedClass has no resources of its own.
840 bool HasVariants = false;
841 for (std::vector<CodeGenSchedTransition>::const_iterator
842 TI = SCI->Transitions.begin(), TE = SCI->Transitions.end();
844 if (TI->ProcIndices[0] == 0) {
848 IdxIter PIPos = std::find(TI->ProcIndices.begin(),
849 TI->ProcIndices.end(), ProcModel.Index);
850 if (PIPos != TI->ProcIndices.end()) {
856 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
860 // Determine if the SchedClass is actually reachable on this processor. If
861 // not don't try to locate the processor resources, it will fail.
862 // If ProcIndices contains 0, this class applies to all processors.
863 assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
864 if (SCI->ProcIndices[0] != 0) {
865 IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
866 SCI->ProcIndices.end(), ProcModel.Index);
867 if (PIPos == SCI->ProcIndices.end())
870 IdxVec Writes = SCI->Writes;
871 IdxVec Reads = SCI->Reads;
872 if (!SCI->InstRWs.empty()) {
873 // This class has a default ReadWrite list which can be overriden by
874 // InstRW definitions.
875 Record *RWDef = nullptr;
876 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
878 Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
879 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
887 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
891 if (Writes.empty()) {
892 // Check this processor's itinerary class resources.
893 for (RecIter II = ProcModel.ItinRWDefs.begin(),
894 IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
895 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
896 if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef)
898 SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),
903 if (Writes.empty()) {
904 DEBUG(dbgs() << ProcModel.ModelName
905 << " does not have resources for class " << SCI->Name << '\n');
908 // Sum resources across all operand writes.
909 std::vector<MCWriteProcResEntry> WriteProcResources;
910 std::vector<MCWriteLatencyEntry> WriteLatencies;
911 std::vector<std::string> WriterNames;
912 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
913 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
915 SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false,
918 // For each operand, create a latency entry.
919 MCWriteLatencyEntry WLEntry;
921 unsigned WriteID = WriteSeq.back();
922 WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
923 // If this Write is not referenced by a ReadAdvance, don't distinguish it
924 // from other WriteLatency entries.
925 if (!SchedModels.hasReadOfWrite(
926 SchedModels.getSchedWrite(WriteID).TheDef)) {
929 WLEntry.WriteResourceID = WriteID;
931 for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
935 FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);
937 // Mark the parent class as invalid for unsupported write types.
938 if (WriteRes->getValueAsBit("Unsupported")) {
939 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
942 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
943 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
944 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
945 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
947 // Create an entry for each ProcResource listed in WriteRes.
948 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
949 std::vector<int64_t> Cycles =
950 WriteRes->getValueAsListOfInts("ResourceCycles");
952 ExpandProcResources(PRVec, Cycles, ProcModel);
954 for (unsigned PRIdx = 0, PREnd = PRVec.size();
955 PRIdx != PREnd; ++PRIdx) {
956 MCWriteProcResEntry WPREntry;
957 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
958 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
959 WPREntry.Cycles = Cycles[PRIdx];
960 // If this resource is already used in this sequence, add the current
961 // entry's cycles so that the same resource appears to be used
962 // serially, rather than multiple parallel uses. This is important for
963 // in-order machine where the resource consumption is a hazard.
964 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
965 for( ; WPRIdx != WPREnd; ++WPRIdx) {
966 if (WriteProcResources[WPRIdx].ProcResourceIdx
967 == WPREntry.ProcResourceIdx) {
968 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
972 if (WPRIdx == WPREnd)
973 WriteProcResources.push_back(WPREntry);
976 WriteLatencies.push_back(WLEntry);
978 // Create an entry for each operand Read in this SchedClass.
979 // Entries must be sorted first by UseIdx then by WriteResourceID.
980 for (unsigned UseIdx = 0, EndIdx = Reads.size();
981 UseIdx != EndIdx; ++UseIdx) {
982 Record *ReadAdvance =
983 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
987 // Mark the parent class as invalid for unsupported write types.
988 if (ReadAdvance->getValueAsBit("Unsupported")) {
989 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
992 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
994 if (ValidWrites.empty())
995 WriteIDs.push_back(0);
997 for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end();
999 WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false));
1002 std::sort(WriteIDs.begin(), WriteIDs.end());
1003 for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) {
1004 MCReadAdvanceEntry RAEntry;
1005 RAEntry.UseIdx = UseIdx;
1006 RAEntry.WriteResourceID = *WI;
1007 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1008 ReadAdvanceEntries.push_back(RAEntry);
1011 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1012 WriteProcResources.clear();
1013 WriteLatencies.clear();
1014 ReadAdvanceEntries.clear();
1016 // Add the information for this SchedClass to the global tables using basic
1019 // WritePrecRes entries are sorted by ProcResIdx.
1020 std::sort(WriteProcResources.begin(), WriteProcResources.end(),
1021 LessWriteProcResources());
1023 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1024 std::vector<MCWriteProcResEntry>::iterator WPRPos =
1025 std::search(SchedTables.WriteProcResources.begin(),
1026 SchedTables.WriteProcResources.end(),
1027 WriteProcResources.begin(), WriteProcResources.end());
1028 if (WPRPos != SchedTables.WriteProcResources.end())
1029 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1031 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1032 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
1033 WriteProcResources.end());
1035 // Latency entries must remain in operand order.
1036 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1037 std::vector<MCWriteLatencyEntry>::iterator WLPos =
1038 std::search(SchedTables.WriteLatencies.begin(),
1039 SchedTables.WriteLatencies.end(),
1040 WriteLatencies.begin(), WriteLatencies.end());
1041 if (WLPos != SchedTables.WriteLatencies.end()) {
1042 unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
1043 SCDesc.WriteLatencyIdx = idx;
1044 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
1045 if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
1046 std::string::npos) {
1047 SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
1051 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1052 SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
1053 WriteLatencies.begin(),
1054 WriteLatencies.end());
1055 SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
1056 WriterNames.begin(), WriterNames.end());
1058 // ReadAdvanceEntries must remain in operand order.
1059 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1060 std::vector<MCReadAdvanceEntry>::iterator RAPos =
1061 std::search(SchedTables.ReadAdvanceEntries.begin(),
1062 SchedTables.ReadAdvanceEntries.end(),
1063 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
1064 if (RAPos != SchedTables.ReadAdvanceEntries.end())
1065 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1067 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1068 SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
1069 ReadAdvanceEntries.end());
1074 // Emit SchedClass tables for all processors and associated global tables.
1075 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
1077 // Emit global WriteProcResTable.
1078 OS << "\n// {ProcResourceIdx, Cycles}\n"
1079 << "extern const llvm::MCWriteProcResEntry "
1080 << Target << "WriteProcResTable[] = {\n"
1081 << " { 0, 0}, // Invalid\n";
1082 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1083 WPRIdx != WPREnd; ++WPRIdx) {
1084 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1085 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1086 << format("%2d", WPREntry.Cycles) << "}";
1087 if (WPRIdx + 1 < WPREnd)
1089 OS << " // #" << WPRIdx << '\n';
1091 OS << "}; // " << Target << "WriteProcResTable\n";
1093 // Emit global WriteLatencyTable.
1094 OS << "\n// {Cycles, WriteResourceID}\n"
1095 << "extern const llvm::MCWriteLatencyEntry "
1096 << Target << "WriteLatencyTable[] = {\n"
1097 << " { 0, 0}, // Invalid\n";
1098 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1099 WLIdx != WLEnd; ++WLIdx) {
1100 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1101 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1102 << format("%2d", WLEntry.WriteResourceID) << "}";
1103 if (WLIdx + 1 < WLEnd)
1105 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1107 OS << "}; // " << Target << "WriteLatencyTable\n";
1109 // Emit global ReadAdvanceTable.
1110 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1111 << "extern const llvm::MCReadAdvanceEntry "
1112 << Target << "ReadAdvanceTable[] = {\n"
1113 << " {0, 0, 0}, // Invalid\n";
1114 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1115 RAIdx != RAEnd; ++RAIdx) {
1116 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1117 OS << " {" << RAEntry.UseIdx << ", "
1118 << format("%2d", RAEntry.WriteResourceID) << ", "
1119 << format("%2d", RAEntry.Cycles) << "}";
1120 if (RAIdx + 1 < RAEnd)
1122 OS << " // #" << RAIdx << '\n';
1124 OS << "}; // " << Target << "ReadAdvanceTable\n";
1126 // Emit a SchedClass table for each processor.
1127 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1128 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1129 if (!PI->hasInstrSchedModel())
1132 std::vector<MCSchedClassDesc> &SCTab =
1133 SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
1135 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
1136 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1137 OS << "static const llvm::MCSchedClassDesc "
1138 << PI->ModelName << "SchedClasses[] = {\n";
1140 // The first class is always invalid. We no way to distinguish it except by
1141 // name and position.
1142 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
1143 && "invalid class not first");
1144 OS << " {DBGFIELD(\"InvalidSchedClass\") "
1145 << MCSchedClassDesc::InvalidNumMicroOps
1146 << ", 0, 0, 0, 0, 0, 0, 0, 0},\n";
1148 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1149 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1150 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1151 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1152 if (SchedClass.Name.size() < 18)
1153 OS.indent(18 - SchedClass.Name.size());
1154 OS << MCDesc.NumMicroOps
1155 << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
1156 << ", " << format("%2d", MCDesc.WriteProcResIdx)
1157 << ", " << MCDesc.NumWriteProcResEntries
1158 << ", " << format("%2d", MCDesc.WriteLatencyIdx)
1159 << ", " << MCDesc.NumWriteLatencyEntries
1160 << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
1161 << ", " << MCDesc.NumReadAdvanceEntries << "}";
1162 if (SCIdx + 1 < SCEnd)
1164 OS << " // #" << SCIdx << '\n';
1166 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1170 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1171 // For each processor model.
1172 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1173 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1174 // Emit processor resource table.
1175 if (PI->hasInstrSchedModel())
1176 EmitProcessorResources(*PI, OS);
1177 else if(!PI->ProcResourceDefs.empty())
1178 PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines "
1179 "ProcResources without defining WriteRes SchedWriteRes");
1181 // Begin processor itinerary properties
1183 OS << "static const llvm::MCSchedModel " << PI->ModelName << " = {\n";
1184 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
1185 EmitProcessorProp(OS, PI->ModelDef, "MicroOpBufferSize", ',');
1186 EmitProcessorProp(OS, PI->ModelDef, "LoopMicroOpBufferSize", ',');
1187 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
1188 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
1189 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
1191 OS << " " << (bool)(PI->ModelDef ?
1192 PI->ModelDef->getValueAsBit("PostRAScheduler") : 0)
1193 << ", // " << "PostRAScheduler\n";
1195 OS << " " << (bool)(PI->ModelDef ?
1196 PI->ModelDef->getValueAsBit("CompleteModel") : 0)
1197 << ", // " << "CompleteModel\n";
1199 OS << " " << PI->Index << ", // Processor ID\n";
1200 if (PI->hasInstrSchedModel())
1201 OS << " " << PI->ModelName << "ProcResources" << ",\n"
1202 << " " << PI->ModelName << "SchedClasses" << ",\n"
1203 << " " << PI->ProcResourceDefs.size()+1 << ",\n"
1204 << " " << (SchedModels.schedClassEnd()
1205 - SchedModels.schedClassBegin()) << ",\n";
1207 OS << " 0, 0, 0, 0, // No instruction-level machine model.\n";
1208 if (PI->hasItineraries())
1209 OS << " " << PI->ItinsDef->getName() << "};\n";
1211 OS << " nullptr}; // No Itinerary\n";
1216 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
1218 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1219 // Gather and sort processor information
1220 std::vector<Record*> ProcessorList =
1221 Records.getAllDerivedDefinitions("Processor");
1222 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
1224 // Begin processor table
1226 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
1227 << "extern const llvm::SubtargetInfoKV "
1228 << Target << "ProcSchedKV[] = {\n";
1230 // For each processor
1231 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
1233 Record *Processor = ProcessorList[i];
1235 const std::string &Name = Processor->getValueAsString("Name");
1236 const std::string &ProcModelName =
1237 SchedModels.getModelForProc(Processor).ModelName;
1239 // Emit as { "cpu", procinit },
1240 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
1242 // Depending on ''if more in the list'' emit comma
1243 if (++i < N) OS << ",";
1248 // End processor table
1253 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1255 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1256 OS << "#ifdef DBGFIELD\n"
1257 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1259 << "#ifndef NDEBUG\n"
1260 << "#define DBGFIELD(x) x,\n"
1262 << "#define DBGFIELD(x)\n"
1265 if (SchedModels.hasItineraries()) {
1266 std::vector<std::vector<InstrItinerary> > ProcItinLists;
1267 // Emit the stage data
1268 EmitStageAndOperandCycleData(OS, ProcItinLists);
1269 EmitItineraries(OS, ProcItinLists);
1271 OS << "\n// ===============================================================\n"
1272 << "// Data tables for the new per-operand machine model.\n";
1274 SchedClassTables SchedTables;
1275 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1276 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1277 GenSchedClassTables(*PI, SchedTables);
1279 EmitSchedClassTables(SchedTables, OS);
1281 // Emit the processor machine model
1282 EmitProcessorModels(OS);
1283 // Emit the processor lookup data
1284 EmitProcessorLookup(OS);
1286 OS << "#undef DBGFIELD";
1289 void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName,
1291 OS << "unsigned " << ClassName
1292 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1293 << " const TargetSchedModel *SchedModel) const {\n";
1295 std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog");
1296 std::sort(Prologs.begin(), Prologs.end(), LessRecord());
1297 for (std::vector<Record*>::const_iterator
1298 PI = Prologs.begin(), PE = Prologs.end(); PI != PE; ++PI) {
1299 OS << (*PI)->getValueAsString("Code") << '\n';
1301 IdxVec VariantClasses;
1302 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
1303 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
1304 if (SCI->Transitions.empty())
1306 VariantClasses.push_back(SCI->Index);
1308 if (!VariantClasses.empty()) {
1309 OS << " switch (SchedClass) {\n";
1310 for (IdxIter VCI = VariantClasses.begin(), VCE = VariantClasses.end();
1311 VCI != VCE; ++VCI) {
1312 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI);
1313 OS << " case " << *VCI << ": // " << SC.Name << '\n';
1315 for (std::vector<CodeGenSchedTransition>::const_iterator
1316 TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1319 std::set_union(TI->ProcIndices.begin(), TI->ProcIndices.end(),
1320 ProcIndices.begin(), ProcIndices.end(),
1321 std::back_inserter(PI));
1322 ProcIndices.swap(PI);
1324 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1328 OS << "if (SchedModel->getProcessorID() == " << *PI << ") ";
1329 OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName
1331 for (std::vector<CodeGenSchedTransition>::const_iterator
1332 TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1334 if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
1335 TI->ProcIndices.end(), *PI)) {
1339 for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
1341 if (RI != TI->PredTerm.begin())
1343 OS << "(" << (*RI)->getValueAsString("Predicate") << ")";
1346 << " return " << TI->ToClassIdx << "; // "
1347 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n';
1353 if (SC.isInferred())
1354 OS << " return " << SC.Index << ";\n";
1359 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"
1360 << "} // " << ClassName << "::resolveSchedClass\n";
1364 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
1365 // the subtarget features string.
1367 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1368 unsigned NumFeatures,
1369 unsigned NumProcs) {
1370 std::vector<Record*> Features =
1371 Records.getAllDerivedDefinitions("SubtargetFeature");
1372 std::sort(Features.begin(), Features.end(), LessRecord());
1374 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1375 << "// subtarget options.\n"
1378 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
1379 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1380 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
1382 if (Features.empty()) {
1387 OS << " InitMCProcessorInfo(CPU, FS);\n"
1388 << " uint64_t Bits = getFeatureBits();\n";
1390 for (unsigned i = 0; i < Features.size(); i++) {
1392 Record *R = Features[i];
1393 const std::string &Instance = R->getName();
1394 const std::string &Value = R->getValueAsString("Value");
1395 const std::string &Attribute = R->getValueAsString("Attribute");
1397 if (Value=="true" || Value=="false")
1398 OS << " if ((Bits & " << Target << "::"
1399 << Instance << ") != 0) "
1400 << Attribute << " = " << Value << ";\n";
1402 OS << " if ((Bits & " << Target << "::"
1403 << Instance << ") != 0 && "
1404 << Attribute << " < " << Value << ") "
1405 << Attribute << " = " << Value << ";\n";
1412 // SubtargetEmitter::run - Main subtarget enumeration emitter.
1414 void SubtargetEmitter::run(raw_ostream &OS) {
1415 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1417 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1418 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
1420 OS << "namespace llvm {\n";
1421 Enumeration(OS, "SubtargetFeature", true);
1422 OS << "} // End llvm namespace \n";
1423 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1425 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1426 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
1428 OS << "namespace llvm {\n";
1430 OS << "namespace {\n";
1432 unsigned NumFeatures = FeatureKeyValues(OS);
1434 unsigned NumProcs = CPUKeyValues(OS);
1442 // MCInstrInfo initialization routine.
1443 OS << "static inline void Init" << Target
1444 << "MCSubtargetInfo(MCSubtargetInfo *II, "
1445 << "StringRef TT, StringRef CPU, StringRef FS) {\n";
1446 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
1448 OS << Target << "FeatureKV, ";
1452 OS << Target << "SubTypeKV, ";
1455 OS << '\n'; OS.indent(22);
1456 OS << Target << "ProcSchedKV, "
1457 << Target << "WriteProcResTable, "
1458 << Target << "WriteLatencyTable, "
1459 << Target << "ReadAdvanceTable, ";
1460 if (SchedModels.hasItineraries()) {
1461 OS << '\n'; OS.indent(22);
1462 OS << Target << "Stages, "
1463 << Target << "OperandCycles, "
1464 << Target << "ForwardingPaths";
1469 OS << "} // End llvm namespace \n";
1471 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1473 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1474 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
1476 OS << "#include \"llvm/Support/Debug.h\"\n";
1477 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
1478 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1480 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1482 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
1483 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1484 OS << "#undef GET_SUBTARGETINFO_HEADER\n";
1486 std::string ClassName = Target + "GenSubtargetInfo";
1487 OS << "namespace llvm {\n";
1488 OS << "class DFAPacketizer;\n";
1489 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1490 << " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
1491 << "StringRef FS);\n"
1493 << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI,"
1494 << " const TargetSchedModel *SchedModel) const override;\n"
1495 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
1498 OS << "} // End llvm namespace \n";
1500 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1502 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1503 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
1505 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
1506 OS << "namespace llvm {\n";
1507 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1508 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
1509 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
1510 OS << "extern const llvm::MCWriteProcResEntry "
1511 << Target << "WriteProcResTable[];\n";
1512 OS << "extern const llvm::MCWriteLatencyEntry "
1513 << Target << "WriteLatencyTable[];\n";
1514 OS << "extern const llvm::MCReadAdvanceEntry "
1515 << Target << "ReadAdvanceTable[];\n";
1517 if (SchedModels.hasItineraries()) {
1518 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1519 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1520 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1523 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
1524 << "StringRef FS)\n"
1525 << " : TargetSubtargetInfo() {\n"
1526 << " InitMCSubtargetInfo(TT, CPU, FS, ";
1528 OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
1532 OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
1535 OS << '\n'; OS.indent(22);
1536 OS << Target << "ProcSchedKV, "
1537 << Target << "WriteProcResTable, "
1538 << Target << "WriteLatencyTable, "
1539 << Target << "ReadAdvanceTable, ";
1540 OS << '\n'; OS.indent(22);
1541 if (SchedModels.hasItineraries()) {
1542 OS << Target << "Stages, "
1543 << Target << "OperandCycles, "
1544 << Target << "ForwardingPaths";
1549 EmitSchedModelHelpers(ClassName, OS);
1551 OS << "} // End llvm namespace \n";
1553 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1558 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1559 CodeGenTarget CGTarget(RK);
1560 SubtargetEmitter(RK, CGTarget).run(OS);
1563 } // End llvm namespace