1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::deque<CodeGenRegister> &Regs,
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
62 const std::string &ClassName);
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
64 const std::string &ClassName);
66 } // End anonymous namespace
68 // runEnums - Print out enum values for all of the registers.
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70 CodeGenTarget &Target, CodeGenRegBank &Bank) {
71 const auto &Registers = Bank.getRegisters();
73 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace =
77 Registers.front().TheDef->getValueAsString("Namespace");
79 emitSourceFileHeader("Target Register Enum Values", OS);
81 OS << "\n#ifdef GET_REGINFO_ENUM\n";
82 OS << "#undef GET_REGINFO_ENUM\n";
84 OS << "namespace llvm {\n\n";
86 OS << "class MCRegisterClass;\n"
87 << "extern const MCRegisterClass " << Namespace
88 << "MCRegisterClasses[];\n\n";
90 if (!Namespace.empty())
91 OS << "namespace " << Namespace << " {\n";
92 OS << "enum {\n NoRegister,\n";
94 for (const auto &Reg : Registers)
95 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
96 assert(Registers.size() == Registers.back().EnumValue &&
97 "Register enum value mismatch!");
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
100 if (!Namespace.empty())
103 const auto &RegisterClasses = Bank.getRegClasses();
104 if (!RegisterClasses.empty()) {
106 // RegisterClass enums are stored as uint16_t in the tables.
107 assert(RegisterClasses.size() <= 0xffff &&
108 "Too many register classes to fit in tables");
110 OS << "\n// Register classes\n";
111 if (!Namespace.empty())
112 OS << "namespace " << Namespace << " {\n";
114 for (const auto &RC : RegisterClasses)
115 OS << " " << RC.getName() << "RegClassID"
116 << " = " << RC.EnumValue << ",\n";
118 if (!Namespace.empty())
122 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
123 // If the only definition is the default NoRegAltName, we don't need to
125 if (RegAltNameIndices.size() > 1) {
126 OS << "\n// Register alternate name indices\n";
127 if (!Namespace.empty())
128 OS << "namespace " << Namespace << " {\n";
130 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
131 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
132 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
134 if (!Namespace.empty())
138 auto &SubRegIndices = Bank.getSubRegIndices();
139 if (!SubRegIndices.empty()) {
140 OS << "\n// Subregister indices\n";
141 std::string Namespace = SubRegIndices.front().getNamespace();
142 if (!Namespace.empty())
143 OS << "namespace " << Namespace << " {\n";
144 OS << "enum {\n NoSubRegister,\n";
146 for (const auto &Idx : SubRegIndices)
147 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
148 OS << " NUM_TARGET_SUBREGS\n};\n";
149 if (!Namespace.empty())
153 OS << "} // End llvm namespace\n";
154 OS << "#endif // GET_REGINFO_ENUM\n\n";
157 static void printInt(raw_ostream &OS, int Val) {
161 static const char *getMinimalTypeForRange(uint64_t Range) {
162 assert(Range < 0xFFFFFFFFULL && "Enum too large");
170 void RegisterInfoEmitter::
171 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
172 const std::string &ClassName) {
173 unsigned NumRCs = RegBank.getRegClasses().size();
174 unsigned NumSets = RegBank.getNumRegPressureSets();
176 OS << "/// Get the weight in units of pressure for this register class.\n"
177 << "const RegClassWeight &" << ClassName << "::\n"
178 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
179 << " static const RegClassWeight RCWeightTable[] = {\n";
180 for (const auto &RC : RegBank.getRegClasses()) {
181 const CodeGenRegister::Set &Regs = RC.getMembers();
185 std::vector<unsigned> RegUnits;
186 RC.buildRegUnitSet(RegUnits);
187 OS << " {" << (*Regs.begin())->getWeight(RegBank)
188 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
190 OS << "}, \t// " << RC.getName() << "\n";
193 << " return RCWeightTable[RC->getID()];\n"
196 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
197 // bother generating a table.
198 bool RegUnitsHaveUnitWeight = true;
199 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
200 UnitIdx < UnitEnd; ++UnitIdx) {
201 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
202 RegUnitsHaveUnitWeight = false;
204 OS << "/// Get the weight in units of pressure for this register unit.\n"
205 << "unsigned " << ClassName << "::\n"
206 << "getRegUnitWeight(unsigned RegUnit) const {\n"
207 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
208 << " && \"invalid register unit\");\n";
209 if (!RegUnitsHaveUnitWeight) {
210 OS << " static const uint8_t RUWeightTable[] = {\n ";
211 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
212 UnitIdx < UnitEnd; ++UnitIdx) {
213 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
214 assert(RU.Weight < 256 && "RegUnit too heavy");
215 OS << RU.Weight << ", ";
218 << " return RUWeightTable[RegUnit];\n";
221 OS << " // All register units have unit weight.\n"
227 << "// Get the number of dimensions of register pressure.\n"
228 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
229 << " return " << NumSets << ";\n}\n\n";
231 OS << "// Get the name of this register unit pressure set.\n"
232 << "const char *" << ClassName << "::\n"
233 << "getRegPressureSetName(unsigned Idx) const {\n"
234 << " static const char *PressureNameTable[] = {\n";
235 unsigned MaxRegUnitWeight = 0;
236 for (unsigned i = 0; i < NumSets; ++i ) {
237 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
238 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
239 OS << " \"" << RegUnits.Name << "\",\n";
241 OS << " nullptr };\n"
242 << " return PressureNameTable[Idx];\n"
245 OS << "// Get the register unit pressure limit for this dimension.\n"
246 << "// This limit must be adjusted dynamically for reserved registers.\n"
247 << "unsigned " << ClassName << "::\n"
248 << "getRegPressureSetLimit(unsigned Idx) const {\n"
249 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
250 << " PressureLimitTable[] = {\n";
251 for (unsigned i = 0; i < NumSets; ++i ) {
252 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
253 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
254 << RegUnits.Name << "\n";
257 << " return PressureLimitTable[Idx];\n"
260 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
262 // This table may be larger than NumRCs if some register units needed a list
263 // of unit sets that did not correspond to a register class.
264 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
265 std::vector<std::vector<int>> PSets(NumRCUnitSets);
267 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
268 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
269 PSets[i].reserve(PSetIDs.size());
270 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
271 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
272 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
274 std::sort(PSets[i].begin(), PSets[i].end());
275 PSetsSeqs.add(PSets[i]);
280 OS << "/// Table of pressure sets per register class or unit.\n"
281 << "static const int RCSetsTable[] = {\n";
282 PSetsSeqs.emit(OS, printInt, "-1");
285 OS << "/// Get the dimensions of register pressure impacted by this "
286 << "register class.\n"
287 << "/// Returns a -1 terminated array of pressure set IDs\n"
288 << "const int* " << ClassName << "::\n"
289 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
290 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
291 << " RCSetStartTable[] = {\n ";
292 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
293 OS << PSetsSeqs.get(PSets[i]) << ",";
296 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
299 OS << "/// Get the dimensions of register pressure impacted by this "
300 << "register unit.\n"
301 << "/// Returns a -1 terminated array of pressure set IDs\n"
302 << "const int* " << ClassName << "::\n"
303 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
304 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
305 << " && \"invalid register unit\");\n";
306 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
307 << " RUSetStartTable[] = {\n ";
308 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
309 UnitIdx < UnitEnd; ++UnitIdx) {
310 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
314 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
318 void RegisterInfoEmitter::EmitRegMappingTables(
319 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
320 // Collect all information about dwarf register numbers
321 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
322 DwarfRegNumsMapTy DwarfRegNums;
324 // First, just pull all provided information to the map
325 unsigned maxLength = 0;
326 for (auto &RE : Regs) {
327 Record *Reg = RE.TheDef;
328 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
329 maxLength = std::max((size_t)maxLength, RegNums.size());
330 if (DwarfRegNums.count(Reg))
331 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
332 getQualifiedName(Reg) + "specified multiple times");
333 DwarfRegNums[Reg] = RegNums;
339 // Now we know maximal length of number list. Append -1's, where needed
340 for (DwarfRegNumsMapTy::iterator
341 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
342 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
343 I->second.push_back(-1);
345 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
347 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
349 // Emit reverse information about the dwarf register numbers.
350 for (unsigned j = 0; j < 2; ++j) {
351 for (unsigned i = 0, e = maxLength; i != e; ++i) {
352 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
353 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
354 OS << i << "Dwarf2L[]";
359 // Store the mapping sorted by the LLVM reg num so lookup can be done
360 // with a binary search.
361 std::map<uint64_t, Record*> Dwarf2LMap;
362 for (DwarfRegNumsMapTy::iterator
363 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
364 int DwarfRegNo = I->second[i];
367 Dwarf2LMap[DwarfRegNo] = I->first;
370 for (std::map<uint64_t, Record*>::iterator
371 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
372 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
380 // We have to store the size in a const global, it's used in multiple
382 OS << "extern const unsigned " << Namespace
383 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
385 OS << " = array_lengthof(" << Namespace
386 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
393 for (auto &RE : Regs) {
394 Record *Reg = RE.TheDef;
395 const RecordVal *V = Reg->getValue("DwarfAlias");
396 if (!V || !V->getValue())
399 DefInit *DI = cast<DefInit>(V->getValue());
400 Record *Alias = DI->getDef();
401 DwarfRegNums[Reg] = DwarfRegNums[Alias];
404 // Emit information about the dwarf register numbers.
405 for (unsigned j = 0; j < 2; ++j) {
406 for (unsigned i = 0, e = maxLength; i != e; ++i) {
407 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
408 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
409 OS << i << "L2Dwarf[]";
412 // Store the mapping sorted by the Dwarf reg num so lookup can be done
413 // with a binary search.
414 for (DwarfRegNumsMapTy::iterator
415 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
416 int RegNo = I->second[i];
417 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
420 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
428 // We have to store the size in a const global, it's used in multiple
430 OS << "extern const unsigned " << Namespace
431 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
433 OS << " = array_lengthof(" << Namespace
434 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
441 void RegisterInfoEmitter::EmitRegMapping(
442 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
443 // Emit the initializer so the tables from EmitRegMappingTables get wired up
444 // to the MCRegisterInfo object.
445 unsigned maxLength = 0;
446 for (auto &RE : Regs) {
447 Record *Reg = RE.TheDef;
448 maxLength = std::max((size_t)maxLength,
449 Reg->getValueAsListOfInts("DwarfNumbers").size());
455 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
457 // Emit reverse information about the dwarf register numbers.
458 for (unsigned j = 0; j < 2; ++j) {
461 OS << "DwarfFlavour";
466 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
468 for (unsigned i = 0, e = maxLength; i != e; ++i) {
469 OS << " case " << i << ":\n";
474 raw_string_ostream(Tmp) << Namespace
475 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
477 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
488 // Emit information about the dwarf register numbers.
489 for (unsigned j = 0; j < 2; ++j) {
492 OS << "DwarfFlavour";
497 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
499 for (unsigned i = 0, e = maxLength; i != e; ++i) {
500 OS << " case " << i << ":\n";
505 raw_string_ostream(Tmp) << Namespace
506 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
508 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
520 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
521 // Width is the number of bits per hex number.
522 static void printBitVectorAsHex(raw_ostream &OS,
523 const BitVector &Bits,
525 assert(Width <= 32 && "Width too large");
526 unsigned Digits = (Width + 3) / 4;
527 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
529 for (unsigned j = 0; j != Width && i + j != e; ++j)
530 Value |= Bits.test(i + j) << j;
531 OS << format("0x%0*x, ", Digits, Value);
535 // Helper to emit a set of bits into a constant byte array.
536 class BitVectorEmitter {
539 void add(unsigned v) {
540 if (v >= Values.size())
541 Values.resize(((v/8)+1)*8); // Round up to the next byte.
545 void print(raw_ostream &OS) {
546 printBitVectorAsHex(OS, Values, 8);
550 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
551 OS << getEnumName(VT);
554 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
555 OS << Idx->EnumValue;
558 // Differentially encoded register and regunit lists allow for better
559 // compression on regular register banks. The sequence is computed from the
560 // differential list as:
563 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
565 // The initial value depends on the specific list. The list is terminated by a
566 // 0 differential which means we can't encode repeated elements.
568 typedef SmallVector<uint16_t, 4> DiffVec;
570 // Differentially encode a sequence of numbers into V. The starting value and
571 // terminating 0 are not added to V, so it will have the same size as List.
573 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
574 assert(V.empty() && "Clear DiffVec before diffEncode.");
575 uint16_t Val = uint16_t(InitVal);
576 for (unsigned i = 0; i != List.size(); ++i) {
577 uint16_t Cur = List[i];
578 V.push_back(Cur - Val);
584 template<typename Iter>
586 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
587 assert(V.empty() && "Clear DiffVec before diffEncode.");
588 uint16_t Val = uint16_t(InitVal);
589 for (Iter I = Begin; I != End; ++I) {
590 uint16_t Cur = (*I)->EnumValue;
591 V.push_back(Cur - Val);
597 static void printDiff16(raw_ostream &OS, uint16_t Val) {
601 // Try to combine Idx's compose map into Vec if it is compatible.
602 // Return false if it's not possible.
603 static bool combine(const CodeGenSubRegIndex *Idx,
604 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
605 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
606 for (CodeGenSubRegIndex::CompMap::const_iterator
607 I = Map.begin(), E = Map.end(); I != E; ++I) {
608 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
609 if (Entry && Entry != I->second)
613 // All entries are compatible. Make it so.
614 for (CodeGenSubRegIndex::CompMap::const_iterator
615 I = Map.begin(), E = Map.end(); I != E; ++I)
616 Vec[I->first->EnumValue - 1] = I->second;
621 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
622 CodeGenRegBank &RegBank,
623 const std::string &ClName) {
624 const auto &SubRegIndices = RegBank.getSubRegIndices();
625 OS << "unsigned " << ClName
626 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
628 // Many sub-register indexes are composition-compatible, meaning that
630 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
632 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
633 // The illegal entries can be use as wildcards to compress the table further.
635 // Map each Sub-register index to a compatible table row.
636 SmallVector<unsigned, 4> RowMap;
637 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
639 auto SubRegIndicesSize =
640 std::distance(SubRegIndices.begin(), SubRegIndices.end());
641 for (const auto &Idx : SubRegIndices) {
642 unsigned Found = ~0u;
643 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
644 if (combine(&Idx, Rows[r])) {
651 Rows.resize(Found + 1);
652 Rows.back().resize(SubRegIndicesSize);
653 combine(&Idx, Rows.back());
655 RowMap.push_back(Found);
658 // Output the row map if there is multiple rows.
659 if (Rows.size() > 1) {
660 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
661 << SubRegIndicesSize << "] = {\n ";
662 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
663 OS << RowMap[i] << ", ";
668 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
669 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
670 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
672 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
674 OS << Rows[r][i]->EnumValue << ", ";
681 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
682 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
684 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
686 OS << " return Rows[0][IdxB];\n";
691 // runMCDesc - Print out MC register descriptions.
694 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
695 CodeGenRegBank &RegBank) {
696 emitSourceFileHeader("MC Register Information", OS);
698 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
699 OS << "#undef GET_REGINFO_MC_DESC\n";
701 const auto &Regs = RegBank.getRegisters();
703 auto &SubRegIndices = RegBank.getSubRegIndices();
704 // The lists of sub-registers and super-registers go in the same array. That
705 // allows us to share suffixes.
706 typedef std::vector<const CodeGenRegister*> RegVec;
708 // Differentially encoded lists.
709 SequenceToOffsetTable<DiffVec> DiffSeqs;
710 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
711 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
712 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
713 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
715 // Keep track of sub-register names as well. These are not differentially
717 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
718 SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
719 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
721 SequenceToOffsetTable<std::string> RegStrings;
723 // Precompute register lists for the SequenceToOffsetTable.
725 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
726 const auto &Reg = *I;
727 RegStrings.add(Reg.getName());
729 // Compute the ordered sub-register list.
730 SetVector<const CodeGenRegister*> SR;
731 Reg.addSubRegsPreOrder(SR, RegBank);
732 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
733 DiffSeqs.add(SubRegLists[i]);
735 // Compute the corresponding sub-register indexes.
736 SubRegIdxVec &SRIs = SubRegIdxLists[i];
737 for (unsigned j = 0, je = SR.size(); j != je; ++j)
738 SRIs.push_back(Reg.getSubRegIndex(SR[j]));
739 SubRegIdxSeqs.add(SRIs);
741 // Super-registers are already computed.
742 const RegVec &SuperRegList = Reg.getSuperRegs();
743 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
745 DiffSeqs.add(SuperRegLists[i]);
747 // Differentially encode the register unit list, seeded by register number.
748 // First compute a scale factor that allows more diff-lists to be reused:
753 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
754 // value for the differential decoder is the register number multiplied by
757 // Check the neighboring registers for arithmetic progressions.
758 unsigned ScaleA = ~0u, ScaleB = ~0u;
759 ArrayRef<unsigned> RUs = Reg.getNativeRegUnits();
760 if (I != Regs.begin() &&
761 std::prev(I)->getNativeRegUnits().size() == RUs.size())
762 ScaleB = RUs.front() - std::prev(I)->getNativeRegUnits().front();
763 if (std::next(I) != Regs.end() &&
764 std::next(I)->getNativeRegUnits().size() == RUs.size())
765 ScaleA = std::next(I)->getNativeRegUnits().front() - RUs.front();
766 unsigned Scale = std::min(ScaleB, ScaleA);
767 // Default the scale to 0 if it can't be encoded in 4 bits.
770 RegUnitInitScale[i] = Scale;
771 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
775 // Compute the final layout of the sequence table.
777 SubRegIdxSeqs.layout();
779 OS << "namespace llvm {\n\n";
781 const std::string &TargetName = Target.getName();
783 // Emit the shared table of differential lists.
784 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
785 DiffSeqs.emit(OS, printDiff16);
788 // Emit the table of sub-register indexes.
789 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
790 SubRegIdxSeqs.emit(OS, printSubRegIndex);
793 // Emit the table of sub-register index sizes.
794 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
795 << TargetName << "SubRegIdxRanges[] = {\n";
796 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
797 for (const auto &Idx : SubRegIndices) {
798 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
799 << Idx.getName() << "\n";
803 // Emit the string table.
805 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
806 RegStrings.emit(OS, printChar);
809 OS << "extern const MCRegisterDesc " << TargetName
810 << "RegDesc[] = { // Descriptors\n";
811 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
813 // Emit the register descriptors now.
815 for (const auto &Reg : Regs) {
816 OS << " { " << RegStrings.get(Reg.getName()) << ", "
817 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
818 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
819 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << " },\n";
822 OS << "};\n\n"; // End of register descriptors...
824 // Emit the table of register unit roots. Each regunit has one or two root
826 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
827 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
828 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
829 assert(!Roots.empty() && "All regunits must have a root register.");
830 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
831 OS << " { " << getQualifiedName(Roots.front()->TheDef);
832 for (unsigned r = 1; r != Roots.size(); ++r)
833 OS << ", " << getQualifiedName(Roots[r]->TheDef);
838 const auto &RegisterClasses = RegBank.getRegClasses();
840 // Loop over all of the register classes... emitting each one.
841 OS << "namespace { // Register classes...\n";
843 SequenceToOffsetTable<std::string> RegClassStrings;
845 // Emit the register enum value arrays for each RegisterClass
846 for (const auto &RC : RegisterClasses) {
847 ArrayRef<Record*> Order = RC.getOrder();
849 // Give the register class a legal C name if it's anonymous.
850 std::string Name = RC.getName();
852 RegClassStrings.add(Name);
854 // Emit the register list now.
855 OS << " // " << Name << " Register Class...\n"
856 << " const MCPhysReg " << Name
858 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
859 Record *Reg = Order[i];
860 OS << getQualifiedName(Reg) << ", ";
864 OS << " // " << Name << " Bit set.\n"
865 << " const uint8_t " << Name
867 BitVectorEmitter BVE;
868 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
869 Record *Reg = Order[i];
870 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
878 RegClassStrings.layout();
879 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
880 RegClassStrings.emit(OS, printChar);
883 OS << "extern const MCRegisterClass " << TargetName
884 << "MCRegisterClasses[] = {\n";
886 for (const auto &RC : RegisterClasses) {
887 // Asserts to make sure values will fit in table assuming types from
889 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
890 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
891 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
893 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
894 << RegClassStrings.get(RC.getName()) << ", "
895 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
896 << RC.getQualifiedName() + "RegClassID" << ", "
897 << RC.SpillSize/8 << ", "
898 << RC.SpillAlignment/8 << ", "
899 << RC.CopyCost << ", "
900 << RC.Allocatable << " },\n";
905 EmitRegMappingTables(OS, Regs, false);
907 // Emit Reg encoding table
908 OS << "extern const uint16_t " << TargetName;
909 OS << "RegEncodingTable[] = {\n";
910 // Add entry for NoRegister
912 for (const auto &RE : Regs) {
913 Record *Reg = RE.TheDef;
914 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
916 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
917 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
918 Value |= (uint64_t)B->getValue() << b;
920 OS << " " << Value << ",\n";
922 OS << "};\n"; // End of HW encoding table
924 // MCRegisterInfo initialization routine.
925 OS << "static inline void Init" << TargetName
926 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
927 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
929 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
930 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
931 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
932 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
933 << TargetName << "RegStrings, " << TargetName << "RegClassStrings, "
934 << TargetName << "SubRegIdxLists, "
935 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
936 << TargetName << "SubRegIdxRanges, " << TargetName
937 << "RegEncodingTable);\n\n";
939 EmitRegMapping(OS, Regs, false);
943 OS << "} // End llvm namespace\n";
944 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
948 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
949 CodeGenRegBank &RegBank) {
950 emitSourceFileHeader("Register Information Header Fragment", OS);
952 OS << "\n#ifdef GET_REGINFO_HEADER\n";
953 OS << "#undef GET_REGINFO_HEADER\n";
955 const std::string &TargetName = Target.getName();
956 std::string ClassName = TargetName + "GenRegisterInfo";
958 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
960 OS << "namespace llvm {\n\n";
962 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
963 << " explicit " << ClassName
964 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
965 << " bool needsStackRealignment(const MachineFunction &) const override\n"
966 << " { return false; }\n";
967 if (!RegBank.getSubRegIndices().empty()) {
968 OS << " unsigned composeSubRegIndicesImpl"
969 << "(unsigned, unsigned) const override;\n"
970 << " const TargetRegisterClass *getSubClassWithSubReg"
971 << "(const TargetRegisterClass*, unsigned) const override;\n";
973 OS << " const RegClassWeight &getRegClassWeight("
974 << "const TargetRegisterClass *RC) const override;\n"
975 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
976 << " unsigned getNumRegPressureSets() const override;\n"
977 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
978 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
979 << " const int *getRegClassPressureSets("
980 << "const TargetRegisterClass *RC) const override;\n"
981 << " const int *getRegUnitPressureSets("
982 << "unsigned RegUnit) const override;\n"
985 const auto &RegisterClasses = RegBank.getRegClasses();
987 if (!RegisterClasses.empty()) {
988 OS << "namespace " << RegisterClasses.front().Namespace
989 << " { // Register classes\n";
991 for (const auto &RC : RegisterClasses) {
992 const std::string &Name = RC.getName();
994 // Output the extern for the instance.
995 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
997 OS << "} // end of namespace " << TargetName << "\n\n";
999 OS << "} // End llvm namespace\n";
1000 OS << "#endif // GET_REGINFO_HEADER\n\n";
1004 // runTargetDesc - Output the target register and register file descriptions.
1007 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1008 CodeGenRegBank &RegBank){
1009 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1011 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1012 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1014 OS << "namespace llvm {\n\n";
1016 // Get access to MCRegisterClass data.
1017 OS << "extern const MCRegisterClass " << Target.getName()
1018 << "MCRegisterClasses[];\n";
1020 // Start out by emitting each of the register classes.
1021 const auto &RegisterClasses = RegBank.getRegClasses();
1022 const auto &SubRegIndices = RegBank.getSubRegIndices();
1024 // Collect all registers belonging to any allocatable class.
1025 std::set<Record*> AllocatableRegs;
1027 // Collect allocatable registers.
1028 for (const auto &RC : RegisterClasses) {
1029 ArrayRef<Record*> Order = RC.getOrder();
1032 AllocatableRegs.insert(Order.begin(), Order.end());
1035 // Build a shared array of value types.
1036 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1037 for (const auto &RC : RegisterClasses)
1040 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1041 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1044 // Emit SubRegIndex names, skipping 0.
1045 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1047 for (const auto &Idx : SubRegIndices) {
1048 OS << Idx.getName();
1053 // Emit SubRegIndex lane masks, including 0.
1054 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1055 for (const auto &Idx : SubRegIndices) {
1056 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
1062 // Now that all of the structs have been emitted, emit the instances.
1063 if (!RegisterClasses.empty()) {
1064 OS << "\nstatic const TargetRegisterClass *const "
1065 << "NullRegClasses[] = { nullptr };\n\n";
1067 // Emit register class bit mask tables. The first bit mask emitted for a
1068 // register class, RC, is the set of sub-classes, including RC itself.
1070 // If RC has super-registers, also create a list of subreg indices and bit
1071 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1072 // SuperRC, that satisfies:
1074 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1076 // The 0-terminated list of subreg indices starts at:
1078 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1080 // The corresponding bitmasks follow the sub-class mask in memory. Each
1081 // mask has RCMaskWords uint32_t entries.
1083 // Every bit mask present in the list has at least one bit set.
1085 // Compress the sub-reg index lists.
1086 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1087 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1088 SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
1089 BitVector MaskBV(RegisterClasses.size());
1091 for (const auto &RC : RegisterClasses) {
1092 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1093 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1095 // Emit super-reg class masks for any relevant SubRegIndices that can
1097 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1098 for (auto &Idx : SubRegIndices) {
1100 RC.getSuperRegClasses(&Idx, MaskBV);
1103 SRIList.push_back(&Idx);
1105 printBitVectorAsHex(OS, MaskBV, 32);
1106 OS << "// " << Idx.getName();
1108 SuperRegIdxSeqs.add(SRIList);
1112 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1113 SuperRegIdxSeqs.layout();
1114 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1117 // Emit NULL terminated super-class lists.
1118 for (const auto &RC : RegisterClasses) {
1119 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1121 // Skip classes without supers. We can reuse NullRegClasses.
1125 OS << "static const TargetRegisterClass *const "
1126 << RC.getName() << "Superclasses[] = {\n";
1127 for (const auto *Super : Supers)
1128 OS << " &" << Super->getQualifiedName() << "RegClass,\n";
1129 OS << " nullptr\n};\n\n";
1133 for (const auto &RC : RegisterClasses) {
1134 if (!RC.AltOrderSelect.empty()) {
1135 OS << "\nstatic inline unsigned " << RC.getName()
1136 << "AltOrderSelect(const MachineFunction &MF) {"
1137 << RC.AltOrderSelect << "}\n\n"
1138 << "static ArrayRef<MCPhysReg> " << RC.getName()
1139 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1140 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1141 ArrayRef<Record*> Elems = RC.getOrder(oi);
1142 if (!Elems.empty()) {
1143 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1144 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1145 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1149 OS << " const MCRegisterClass &MCR = " << Target.getName()
1150 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1151 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1152 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1153 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1154 if (RC.getOrder(oi).empty())
1155 OS << "),\n ArrayRef<MCPhysReg>(";
1157 OS << "),\n makeArrayRef(AltOrder" << oi;
1158 OS << ")\n };\n const unsigned Select = " << RC.getName()
1159 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1160 << ");\n return Order[Select];\n}\n";
1164 // Now emit the actual value-initialized register class instances.
1165 OS << "\nnamespace " << RegisterClasses.front().Namespace
1166 << " { // Register class instances\n";
1168 for (const auto &RC : RegisterClasses) {
1169 OS << " extern const TargetRegisterClass " << RC.getName()
1170 << "RegClass = {\n " << '&' << Target.getName()
1171 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1172 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
1173 << "SubClassMask,\n SuperRegIdxSeqs + "
1174 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1175 if (RC.getSuperClasses().empty())
1176 OS << "NullRegClasses,\n ";
1178 OS << RC.getName() << "Superclasses,\n ";
1179 if (RC.AltOrderSelect.empty())
1182 OS << RC.getName() << "GetRawAllocationOrder\n";
1189 OS << "\nnamespace {\n";
1190 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1191 for (const auto &RC : RegisterClasses)
1192 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1194 OS << "}\n"; // End of anonymous namespace...
1196 // Emit extra information about registers.
1197 const std::string &TargetName = Target.getName();
1198 OS << "\nstatic const TargetRegisterInfoDesc "
1199 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1200 OS << " { 0, 0 },\n";
1202 const auto &Regs = RegBank.getRegisters();
1203 for (const auto &Reg : Regs) {
1205 OS << Reg.CostPerUse << ", "
1206 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1208 OS << "};\n"; // End of register descriptors...
1211 std::string ClassName = Target.getName() + "GenRegisterInfo";
1213 auto SubRegIndicesSize =
1214 std::distance(SubRegIndices.begin(), SubRegIndices.end());
1216 if (!SubRegIndices.empty())
1217 emitComposeSubRegIndices(OS, RegBank, ClassName);
1219 // Emit getSubClassWithSubReg.
1220 if (!SubRegIndices.empty()) {
1221 OS << "const TargetRegisterClass *" << ClassName
1222 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1224 // Use the smallest type that can hold a regclass ID with room for a
1226 if (RegisterClasses.size() < UINT8_MAX)
1227 OS << " static const uint8_t Table[";
1228 else if (RegisterClasses.size() < UINT16_MAX)
1229 OS << " static const uint16_t Table[";
1231 PrintFatalError("Too many register classes.");
1232 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1233 for (const auto &RC : RegisterClasses) {
1234 OS << " {\t// " << RC.getName() << "\n";
1235 for (auto &Idx : SubRegIndices) {
1236 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1237 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1238 << " -> " << SRC->getName() << "\n";
1240 OS << " 0,\t// " << Idx.getName() << "\n";
1244 OS << " };\n assert(RC && \"Missing regclass\");\n"
1245 << " if (!Idx) return RC;\n --Idx;\n"
1246 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1247 << " unsigned TV = Table[RC->getID()][Idx];\n"
1248 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1251 EmitRegUnitPressure(OS, RegBank, ClassName);
1253 // Emit the constructor of the class...
1254 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1255 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1256 OS << "extern const char " << TargetName << "RegStrings[];\n";
1257 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1258 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1259 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1260 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1261 << TargetName << "SubRegIdxRanges[];\n";
1262 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1264 EmitRegMappingTables(OS, Regs, true);
1266 OS << ClassName << "::\n" << ClassName
1267 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1268 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1269 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1270 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1271 OS.write_hex(RegBank.CoveringLanes);
1273 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1274 << ", RA, PC,\n " << TargetName
1275 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1276 << " " << TargetName << "RegUnitRoots,\n"
1277 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1278 << " " << TargetName << "RegDiffLists,\n"
1279 << " " << TargetName << "RegStrings,\n"
1280 << " " << TargetName << "RegClassStrings,\n"
1281 << " " << TargetName << "SubRegIdxLists,\n"
1282 << " " << SubRegIndicesSize + 1 << ",\n"
1283 << " " << TargetName << "SubRegIdxRanges,\n"
1284 << " " << TargetName << "RegEncodingTable);\n\n";
1286 EmitRegMapping(OS, Regs, true);
1291 // Emit CalleeSavedRegs information.
1292 std::vector<Record*> CSRSets =
1293 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1294 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1295 Record *CSRSet = CSRSets[i];
1296 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1297 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1299 // Emit the *_SaveList list of callee-saved registers.
1300 OS << "static const MCPhysReg " << CSRSet->getName()
1301 << "_SaveList[] = { ";
1302 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1303 OS << getQualifiedName((*Regs)[r]) << ", ";
1306 // Emit the *_RegMask bit mask of call-preserved registers.
1307 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1309 // Check for an optional OtherPreserved set.
1310 // Add those registers to RegMask, but not to SaveList.
1311 if (DagInit *OPDag =
1312 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1313 SetTheory::RecSet OPSet;
1314 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1315 Covered |= RegBank.computeCoveredRegisters(
1316 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1319 OS << "static const uint32_t " << CSRSet->getName()
1320 << "_RegMask[] = { ";
1321 printBitVectorAsHex(OS, Covered, 32);
1326 OS << "} // End llvm namespace\n";
1327 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1330 void RegisterInfoEmitter::run(raw_ostream &OS) {
1331 CodeGenTarget Target(Records);
1332 CodeGenRegBank &RegBank = Target.getRegBank();
1333 RegBank.computeDerivedInfo();
1335 runEnums(OS, Target, RegBank);
1336 runMCDesc(OS, Target, RegBank);
1337 runTargetHeader(OS, Target, RegBank);
1338 runTargetDesc(OS, Target, RegBank);
1343 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1344 RegisterInfoEmitter(RK).run(OS);
1347 } // End llvm namespace