1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Format.h"
28 // runEnums - Print out enum values for all of the registers.
30 RegisterInfoEmitter::runEnums(raw_ostream &OS,
31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
36 EmitSourceFileHeader("Target Register Enum Values", OS);
38 OS << "\n#ifdef GET_REGINFO_ENUM\n";
39 OS << "#undef GET_REGINFO_ENUM\n";
41 OS << "namespace llvm {\n\n";
43 OS << "class MCRegisterClass;\n"
44 << "extern const MCRegisterClass " << Namespace
45 << "MCRegisterClasses[];\n\n";
47 if (!Namespace.empty())
48 OS << "namespace " << Namespace << " {\n";
49 OS << "enum {\n NoRegister,\n";
51 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
52 OS << " " << Registers[i]->getName() << " = " <<
53 Registers[i]->EnumValue << ",\n";
54 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
55 "Register enum value mismatch!");
56 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
58 if (!Namespace.empty())
61 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
62 if (!RegisterClasses.empty()) {
63 OS << "\n// Register classes\n";
64 if (!Namespace.empty())
65 OS << "namespace " << Namespace << " {\n";
67 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
69 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
73 if (!Namespace.empty())
77 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
78 // If the only definition is the default NoRegAltName, we don't need to
80 if (RegAltNameIndices.size() > 1) {
81 OS << "\n// Register alternate name indices\n";
82 if (!Namespace.empty())
83 OS << "namespace " << Namespace << " {\n";
85 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
86 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
87 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
89 if (!Namespace.empty())
94 OS << "} // End llvm namespace \n";
95 OS << "#endif // GET_REGINFO_ENUM\n\n";
99 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
100 const std::vector<CodeGenRegister*> &Regs,
103 // Collect all information about dwarf register numbers
104 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
105 DwarfRegNumsMapTy DwarfRegNums;
107 // First, just pull all provided information to the map
108 unsigned maxLength = 0;
109 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
110 Record *Reg = Regs[i]->TheDef;
111 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
112 maxLength = std::max((size_t)maxLength, RegNums.size());
113 if (DwarfRegNums.count(Reg))
114 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
115 << "specified multiple times\n";
116 DwarfRegNums[Reg] = RegNums;
122 // Now we know maximal length of number list. Append -1's, where needed
123 for (DwarfRegNumsMapTy::iterator
124 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
125 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
126 I->second.push_back(-1);
128 // Emit reverse information about the dwarf register numbers.
129 for (unsigned j = 0; j < 2; ++j) {
132 OS << "DwarfFlavour";
137 << " assert(0 && \"Unknown DWARF flavour\");\n"
140 for (unsigned i = 0, e = maxLength; i != e; ++i) {
141 OS << " case " << i << ":\n";
142 for (DwarfRegNumsMapTy::iterator
143 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
144 int DwarfRegNo = I->second[i];
150 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
151 << getQualifiedName(I->first) << ", ";
163 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
164 Record *Reg = Regs[i]->TheDef;
165 const RecordVal *V = Reg->getValue("DwarfAlias");
166 if (!V || !V->getValue())
169 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
170 Record *Alias = DI->getDef();
171 DwarfRegNums[Reg] = DwarfRegNums[Alias];
174 // Emit information about the dwarf register numbers.
175 for (unsigned j = 0; j < 2; ++j) {
178 OS << "DwarfFlavour";
183 << " assert(0 && \"Unknown DWARF flavour\");\n"
186 for (unsigned i = 0, e = maxLength; i != e; ++i) {
187 OS << " case " << i << ":\n";
188 // Sort by name to get a stable order.
189 for (DwarfRegNumsMapTy::iterator
190 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
191 int RegNo = I->second[i];
195 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
209 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
210 // Width is the number of bits per hex number.
211 static void printBitVectorAsHex(raw_ostream &OS,
212 const BitVector &Bits,
214 assert(Width <= 32 && "Width too large");
215 unsigned Digits = (Width + 3) / 4;
216 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
218 for (unsigned j = 0; j != Width && i + j != e; ++j)
219 Value |= Bits.test(i + j) << j;
220 OS << format("0x%0*x, ", Digits, Value);
224 // Helper to emit a set of bits into a constant byte array.
225 class BitVectorEmitter {
228 void add(unsigned v) {
229 if (v >= Values.size())
230 Values.resize(((v/8)+1)*8); // Round up to the next byte.
234 void print(raw_ostream &OS) {
235 printBitVectorAsHex(OS, Values, 8);
240 // runMCDesc - Print out MC register descriptions.
243 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
244 CodeGenRegBank &RegBank) {
245 EmitSourceFileHeader("MC Register Information", OS);
247 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
248 OS << "#undef GET_REGINFO_MC_DESC\n";
250 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
251 RegBank.computeOverlaps(Overlaps);
253 OS << "namespace llvm {\n\n";
255 const std::string &TargetName = Target.getName();
257 OS << "\nnamespace {\n";
259 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
261 // Emit an overlap list for all registers.
262 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
263 const CodeGenRegister *Reg = Regs[i];
264 const CodeGenRegister::Set &O = Overlaps[Reg];
265 // Move Reg to the front so TRI::getAliasSet can share the list.
266 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
267 << getQualifiedName(Reg->TheDef) << ", ";
268 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
271 OS << getQualifiedName((*I)->TheDef) << ", ";
275 // Emit the empty sub-registers list
276 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
277 // Loop over all of the registers which have sub-registers, emitting the
278 // sub-registers list to memory.
279 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
280 const CodeGenRegister &Reg = *Regs[i];
281 if (Reg.getSubRegs().empty())
283 // getSubRegs() orders by SubRegIndex. We want a topological order.
284 SetVector<CodeGenRegister*> SR;
285 Reg.addSubRegsPreOrder(SR);
286 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
287 for (unsigned j = 0, je = SR.size(); j != je; ++j)
288 OS << getQualifiedName(SR[j]->TheDef) << ", ";
292 // Emit the empty super-registers list
293 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
294 // Loop over all of the registers which have super-registers, emitting the
295 // super-registers list to memory.
296 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
297 const CodeGenRegister &Reg = *Regs[i];
298 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
301 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
302 for (unsigned j = 0, je = SR.size(); j != je; ++j)
303 OS << getQualifiedName(SR[j]->TheDef) << ", ";
306 OS << "}\n"; // End of anonymous namespace...
308 OS << "\nextern const MCRegisterDesc " << TargetName
309 << "RegDesc[] = { // Descriptors\n";
310 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
312 // Now that register alias and sub-registers sets have been emitted, emit the
313 // register descriptors now.
314 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
315 const CodeGenRegister &Reg = *Regs[i];
317 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
318 if (!Reg.getSubRegs().empty())
319 OS << Reg.getName() << "_SubRegsSet,\t";
321 OS << "Empty_SubRegsSet,\t";
322 if (!Reg.getSuperRegs().empty())
323 OS << Reg.getName() << "_SuperRegsSet";
325 OS << "Empty_SuperRegsSet";
328 OS << "};\n\n"; // End of register descriptors...
330 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
332 // Loop over all of the register classes... emitting each one.
333 OS << "namespace { // Register classes...\n";
335 // Emit the register enum value arrays for each RegisterClass
336 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
337 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
338 ArrayRef<Record*> Order = RC.getOrder();
340 // Give the register class a legal C name if it's anonymous.
341 std::string Name = RC.getName();
343 // Emit the register list now.
344 OS << " // " << Name << " Register Class...\n"
345 << " static const unsigned " << Name
347 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
348 Record *Reg = Order[i];
349 OS << getQualifiedName(Reg) << ", ";
353 OS << " // " << Name << " Bit set.\n"
354 << " static const unsigned char " << Name
356 BitVectorEmitter BVE;
357 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
358 Record *Reg = Order[i];
359 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
367 OS << "extern const MCRegisterClass " << TargetName
368 << "MCRegisterClasses[] = {\n";
370 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
371 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
372 OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
373 << '\"' << RC.getName() << "\", "
374 << RC.SpillSize/8 << ", "
375 << RC.SpillAlignment/8 << ", "
376 << RC.CopyCost << ", "
377 << RC.Allocatable << ", "
378 << RC.getName() << ", " << RC.getName() << " + "
379 << RC.getOrder().size() << ", "
380 << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
386 // MCRegisterInfo initialization routine.
387 OS << "static inline void Init" << TargetName
388 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
389 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
390 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
391 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
392 << RegisterClasses.size() << ");\n\n";
394 EmitRegMapping(OS, Regs, false);
399 OS << "} // End llvm namespace \n";
400 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
404 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
405 CodeGenRegBank &RegBank) {
406 EmitSourceFileHeader("Register Information Header Fragment", OS);
408 OS << "\n#ifdef GET_REGINFO_HEADER\n";
409 OS << "#undef GET_REGINFO_HEADER\n";
411 const std::string &TargetName = Target.getName();
412 std::string ClassName = TargetName + "GenRegisterInfo";
414 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
415 OS << "#include <string>\n\n";
417 OS << "namespace llvm {\n\n";
419 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
420 << " explicit " << ClassName
421 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
422 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
423 << " { return false; }\n"
424 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
425 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
426 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
427 << " const TargetRegisterClass *"
428 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
431 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
432 if (!SubRegIndices.empty()) {
433 OS << "\n// Subregister indices\n";
434 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
435 if (!Namespace.empty())
436 OS << "namespace " << Namespace << " {\n";
437 OS << "enum {\n NoSubRegister,\n";
438 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
439 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
440 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
442 if (!Namespace.empty())
446 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
448 if (!RegisterClasses.empty()) {
449 OS << "namespace " << RegisterClasses[0]->Namespace
450 << " { // Register classes\n";
452 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
453 const CodeGenRegisterClass &RC = *RegisterClasses[i];
454 const std::string &Name = RC.getName();
456 // Output the register class definition.
457 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
458 << " " << Name << "Class();\n";
459 if (!RC.AltOrderSelect.empty())
460 OS << " ArrayRef<unsigned> "
461 "getRawAllocationOrder(const MachineFunction&) const;\n";
464 // Output the extern for the instance.
465 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
466 // Output the extern for the pointer to the instance (should remove).
467 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
468 << Name << "RegClass;\n";
470 OS << "} // end of namespace " << TargetName << "\n\n";
472 OS << "} // End llvm namespace \n";
473 OS << "#endif // GET_REGINFO_HEADER\n\n";
477 // runTargetDesc - Output the target register and register file descriptions.
480 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
481 CodeGenRegBank &RegBank){
482 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
484 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
485 OS << "#undef GET_REGINFO_TARGET_DESC\n";
487 OS << "namespace llvm {\n\n";
489 // Get access to MCRegisterClass data.
490 OS << "extern const MCRegisterClass " << Target.getName()
491 << "MCRegisterClasses[];\n";
493 // Start out by emitting each of the register classes.
494 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
496 // Collect all registers belonging to any allocatable class.
497 std::set<Record*> AllocatableRegs;
499 // Collect allocatable registers.
500 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
501 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
502 ArrayRef<Record*> Order = RC.getOrder();
505 AllocatableRegs.insert(Order.begin(), Order.end());
508 OS << "namespace { // Register classes...\n";
510 // Emit the ValueType arrays for each RegisterClass
511 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
512 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
514 // Give the register class a legal C name if it's anonymous.
515 std::string Name = RC.getName() + "VTs";
517 // Emit the register list now.
519 << " Register Class Value Types...\n"
520 << " static const EVT " << Name
522 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
523 OS << getEnumName(RC.VTs[i]) << ", ";
524 OS << "MVT::Other\n };\n\n";
526 OS << "} // end anonymous namespace\n\n";
528 // Now that all of the structs have been emitted, emit the instances.
529 if (!RegisterClasses.empty()) {
530 OS << "namespace " << RegisterClasses[0]->Namespace
531 << " { // Register class instances\n";
532 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
533 OS << " " << RegisterClasses[i]->getName() << "Class\t"
534 << RegisterClasses[i]->getName() << "RegClass;\n";
536 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
538 OS << "\n static const TargetRegisterClass* const "
539 << "NullRegClasses[] = { NULL };\n\n";
541 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
543 if (NumSubRegIndices) {
544 // Compute the super-register classes for each RegisterClass
545 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
546 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
547 for (DenseMap<Record*,Record*>::const_iterator
548 i = RC.SubRegClasses.begin(),
549 e = RC.SubRegClasses.end(); i != e; ++i) {
550 // Find the register class number of i->second for SuperRegClassMap.
551 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
552 assert(RC2 && "Invalid register class in SubRegClasses");
553 SuperRegClassMap[RC2->EnumValue].insert(rc);
557 // Emit the super-register classes for each RegisterClass
558 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
559 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
561 // Give the register class a legal C name if it's anonymous.
562 std::string Name = RC.getName();
565 << " Super-register Classes...\n"
566 << " static const TargetRegisterClass* const "
567 << Name << "SuperRegClasses[] = {\n ";
570 std::map<unsigned, std::set<unsigned> >::iterator I =
571 SuperRegClassMap.find(rc);
572 if (I != SuperRegClassMap.end()) {
573 for (std::set<unsigned>::iterator II = I->second.begin(),
574 EE = I->second.end(); II != EE; ++II) {
575 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
578 OS << "&" << RC2.getQualifiedName() << "RegClass";
583 OS << (!Empty ? ", " : "") << "NULL";
588 // Emit the sub-classes array for each RegisterClass
589 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
590 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
592 // Give the register class a legal C name if it's anonymous.
593 std::string Name = RC.getName();
595 OS << " static const unsigned " << Name << "SubclassMask[] = { ";
596 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
600 // Emit NULL terminated super-class lists.
601 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
602 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
603 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
605 // Skip classes without supers. We can reuse NullRegClasses.
609 OS << " static const TargetRegisterClass* const "
610 << RC.getName() << "Superclasses[] = {\n";
611 for (unsigned i = 0; i != Supers.size(); ++i)
612 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
613 OS << " NULL\n };\n\n";
617 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
618 const CodeGenRegisterClass &RC = *RegisterClasses[i];
619 OS << RC.getName() << "Class::" << RC.getName()
620 << "Class() : TargetRegisterClass(&"
621 << Target.getName() << "MCRegisterClasses["
622 << RC.getName() + "RegClassID" << "], "
623 << RC.getName() + "VTs" << ", "
624 << RC.getName() + "SubclassMask" << ", ";
625 if (RC.getSuperClasses().empty())
626 OS << "NullRegClasses, ";
628 OS << RC.getName() + "Superclasses, ";
629 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
632 if (!RC.AltOrderSelect.empty()) {
633 OS << "\nstatic inline unsigned " << RC.getName()
634 << "AltOrderSelect(const MachineFunction &MF) {"
635 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
636 << RC.getName() << "Class::"
637 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
638 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
639 ArrayRef<Record*> Elems = RC.getOrder(oi);
640 OS << " static const unsigned AltOrder" << oi << "[] = {";
641 for (unsigned elem = 0; elem != Elems.size(); ++elem)
642 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
645 OS << " const MCRegisterClass &MCR = " << Target.getName()
646 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
647 << " static const ArrayRef<unsigned> Order[] = {\n"
648 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
649 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
650 OS << "),\n makeArrayRef(AltOrder" << oi;
651 OS << ")\n };\n const unsigned Select = " << RC.getName()
652 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
653 << ");\n return Order[Select];\n}\n";
660 OS << "\nnamespace {\n";
661 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
662 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
663 OS << " &" << RegisterClasses[i]->getQualifiedName()
666 OS << "}\n"; // End of anonymous namespace...
668 // Emit extra information about registers.
669 const std::string &TargetName = Target.getName();
670 OS << "\n static const TargetRegisterInfoDesc "
671 << TargetName << "RegInfoDesc[] = "
672 << "{ // Extra Descriptors\n";
673 OS << " { 0, 0 },\n";
675 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
676 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
677 const CodeGenRegister &Reg = *Regs[i];
679 OS << Reg.CostPerUse << ", "
680 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
682 OS << " };\n"; // End of register descriptors...
685 // Calculate the mapping of subregister+index pairs to physical registers.
686 // This will also create further anonymous indexes.
687 unsigned NamedIndices = RegBank.getNumNamedIndices();
689 // Emit SubRegIndex names, skipping 0
690 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
691 OS << "\n static const char *const " << TargetName
692 << "SubRegIndexTable[] = { \"";
693 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
694 OS << SubRegIndices[i]->getName();
700 // Emit names of the anonymus subreg indexes.
701 if (SubRegIndices.size() > NamedIndices) {
703 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
704 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
712 std::string ClassName = Target.getName() + "GenRegisterInfo";
714 // Emit the subregister + index mapping function based on the information
716 OS << "unsigned " << ClassName
717 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
718 << " switch (RegNo) {\n"
719 << " default:\n return 0;\n";
720 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
721 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
724 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
725 OS << " switch (Index) {\n";
726 OS << " default: return 0;\n";
727 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
728 ie = SRM.end(); ii != ie; ++ii)
729 OS << " case " << getQualifiedName(ii->first)
730 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
731 OS << " };\n" << " break;\n";
734 OS << " return 0;\n";
737 OS << "unsigned " << ClassName
738 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
739 << " switch (RegNo) {\n"
740 << " default:\n return 0;\n";
741 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
742 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
745 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
746 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
747 ie = SRM.end(); ii != ie; ++ii)
748 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
749 << ") return " << getQualifiedName(ii->first) << ";\n";
750 OS << " return 0;\n";
753 OS << " return 0;\n";
756 // Emit composeSubRegIndices
757 OS << "unsigned " << ClassName
758 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
759 << " switch (IdxA) {\n"
760 << " default:\n return IdxB;\n";
761 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
763 for (unsigned j = 0; j != e; ++j) {
764 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
767 OS << " case " << getQualifiedName(SubRegIndices[i])
768 << ": switch(IdxB) {\n default: return IdxB;\n";
771 OS << " case " << getQualifiedName(SubRegIndices[j])
772 << ": return " << getQualifiedName(Comp) << ";\n";
780 // Emit getSubClassWithSubReg.
781 OS << "const TargetRegisterClass *" << ClassName
782 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
784 if (SubRegIndices.empty()) {
785 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
788 // Use the smallest type that can hold a regclass ID with room for a
790 if (RegisterClasses.size() < UINT8_MAX)
791 OS << " static const uint8_t Table[";
792 else if (RegisterClasses.size() < UINT16_MAX)
793 OS << " static const uint16_t Table[";
795 throw "Too many register classes.";
796 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
797 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
798 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
799 OS << " {\t// " << RC.getName() << "\n";
800 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
801 Record *Idx = SubRegIndices[sri];
802 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
803 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
804 << " -> " << SRC->getName() << "\n";
806 OS << " 0,\t// " << Idx->getName() << "\n";
810 OS << " };\n assert(RC && \"Missing regclass\");\n"
811 << " if (!Idx) return RC;\n --Idx;\n"
812 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
813 << " unsigned TV = Table[RC->getID()][Idx];\n"
814 << " return TV ? getRegClass(TV - 1) : 0;\n";
818 // Emit the constructor of the class...
819 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
821 OS << ClassName << "::" << ClassName
822 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
823 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
824 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
825 << " " << TargetName << "SubRegIndexTable) {\n"
826 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
827 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
828 << RegisterClasses.size() << ");\n\n";
830 EmitRegMapping(OS, Regs, true);
834 OS << "} // End llvm namespace \n";
835 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
838 void RegisterInfoEmitter::run(raw_ostream &OS) {
839 CodeGenTarget Target(Records);
840 CodeGenRegBank &RegBank = Target.getRegBank();
841 RegBank.computeDerivedInfo();
843 runEnums(OS, Target, RegBank);
844 runMCDesc(OS, Target, RegBank);
845 runTargetHeader(OS, Target, RegBank);
846 runTargetDesc(OS, Target, RegBank);