1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/TableGen/Error.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/Format.h"
31 // runEnums - Print out enum values for all of the registers.
32 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
33 CodeGenTarget &Target, CodeGenRegBank &Bank) {
34 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
36 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
37 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
39 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
41 EmitSourceFileHeader("Target Register Enum Values", OS);
43 OS << "\n#ifdef GET_REGINFO_ENUM\n";
44 OS << "#undef GET_REGINFO_ENUM\n";
46 OS << "namespace llvm {\n\n";
48 OS << "class MCRegisterClass;\n"
49 << "extern const MCRegisterClass " << Namespace
50 << "MCRegisterClasses[];\n\n";
52 if (!Namespace.empty())
53 OS << "namespace " << Namespace << " {\n";
54 OS << "enum {\n NoRegister,\n";
56 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
57 OS << " " << Registers[i]->getName() << " = " <<
58 Registers[i]->EnumValue << ",\n";
59 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
60 "Register enum value mismatch!");
61 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
63 if (!Namespace.empty())
66 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
67 if (!RegisterClasses.empty()) {
69 // RegisterClass enums are stored as uint16_t in the tables.
70 assert(RegisterClasses.size() <= 0xffff &&
71 "Too many register classes to fit in tables");
73 OS << "\n// Register classes\n";
74 if (!Namespace.empty())
75 OS << "namespace " << Namespace << " {\n";
77 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
79 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
83 if (!Namespace.empty())
87 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
88 // If the only definition is the default NoRegAltName, we don't need to
90 if (RegAltNameIndices.size() > 1) {
91 OS << "\n// Register alternate name indices\n";
92 if (!Namespace.empty())
93 OS << "namespace " << Namespace << " {\n";
95 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
96 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
97 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
99 if (!Namespace.empty())
103 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
104 if (!SubRegIndices.empty()) {
105 OS << "\n// Subregister indices\n";
106 std::string Namespace =
107 SubRegIndices[0]->getNamespace();
108 if (!Namespace.empty())
109 OS << "namespace " << Namespace << " {\n";
110 OS << "enum {\n NoSubRegister,\n";
111 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
112 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
113 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
114 if (!Namespace.empty())
118 OS << "} // End llvm namespace \n";
119 OS << "#endif // GET_REGINFO_ENUM\n\n";
122 void RegisterInfoEmitter::
123 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
124 const std::string &ClassName) {
125 unsigned NumRCs = RegBank.getRegClasses().size();
126 unsigned NumSets = RegBank.getNumRegPressureSets();
128 OS << "/// Get the weight in units of pressure for this register class.\n"
129 << "const RegClassWeight &" << ClassName << "::\n"
130 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
131 << " static const RegClassWeight RCWeightTable[] = {\n";
132 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
133 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134 const CodeGenRegister::Set &Regs = RC.getMembers();
138 std::vector<unsigned> RegUnits;
139 RC.buildRegUnitSet(RegUnits);
140 OS << " {" << (*Regs.begin())->getWeight(RegBank)
141 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
143 OS << "}, \t// " << RC.getName() << "\n";
146 << " return RCWeightTable[RC->getID()];\n"
150 << "// Get the number of dimensions of register pressure.\n"
151 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
152 << " return " << NumSets << ";\n}\n\n";
154 OS << "// Get the name of this register unit pressure set.\n"
155 << "const char *" << ClassName << "::\n"
156 << "getRegPressureSetName(unsigned Idx) const {\n"
157 << " static const char *PressureNameTable[] = {\n";
158 for (unsigned i = 0; i < NumSets; ++i ) {
159 OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
162 << " return PressureNameTable[Idx];\n"
165 OS << "// Get the register unit pressure limit for this dimension.\n"
166 << "// This limit must be adjusted dynamically for reserved registers.\n"
167 << "unsigned " << ClassName << "::\n"
168 << "getRegPressureSetLimit(unsigned Idx) const {\n"
169 << " static const unsigned PressureLimitTable[] = {\n";
170 for (unsigned i = 0; i < NumSets; ++i ) {
171 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
172 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
173 << ", \t// " << i << ": " << RegUnits.Name << "\n";
176 << " return PressureLimitTable[Idx];\n"
179 OS << "/// Get the dimensions of register pressure "
180 << "impacted by this register class.\n"
181 << "/// Returns a -1 terminated array of pressure set IDs\n"
182 << "const int* " << ClassName << "::\n"
183 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
184 << " static const int RCSetsTable[] = {\n ";
185 std::vector<unsigned> RCSetStarts(NumRCs);
186 for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
187 RCSetStarts[i] = StartIdx;
188 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
189 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
190 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
191 OS << *PSetI << ", ";
194 OS << "-1, \t// " << RegBank.getRegClasses()[i]->getName() << "\n ";
198 OS << " static const unsigned RCSetStartTable[] = {\n ";
199 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
200 OS << RCSetStarts[i] << ",";
203 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
204 << " return &RCSetsTable[SetListStart];\n"
209 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
210 const std::vector<CodeGenRegister*> &Regs,
212 // Collect all information about dwarf register numbers
213 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
214 DwarfRegNumsMapTy DwarfRegNums;
216 // First, just pull all provided information to the map
217 unsigned maxLength = 0;
218 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
219 Record *Reg = Regs[i]->TheDef;
220 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
221 maxLength = std::max((size_t)maxLength, RegNums.size());
222 if (DwarfRegNums.count(Reg))
223 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
224 getQualifiedName(Reg) + "specified multiple times");
225 DwarfRegNums[Reg] = RegNums;
231 // Now we know maximal length of number list. Append -1's, where needed
232 for (DwarfRegNumsMapTy::iterator
233 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
234 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
235 I->second.push_back(-1);
237 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
239 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
241 // Emit reverse information about the dwarf register numbers.
242 for (unsigned j = 0; j < 2; ++j) {
243 for (unsigned i = 0, e = maxLength; i != e; ++i) {
244 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
245 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
246 OS << i << "Dwarf2L[]";
251 // Store the mapping sorted by the LLVM reg num so lookup can be done
252 // with a binary search.
253 std::map<uint64_t, Record*> Dwarf2LMap;
254 for (DwarfRegNumsMapTy::iterator
255 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
256 int DwarfRegNo = I->second[i];
259 Dwarf2LMap[DwarfRegNo] = I->first;
262 for (std::map<uint64_t, Record*>::iterator
263 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
264 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
272 // We have to store the size in a const global, it's used in multiple
274 OS << "extern const unsigned " << Namespace
275 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
277 OS << " = sizeof(" << Namespace
278 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
279 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
285 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
286 Record *Reg = Regs[i]->TheDef;
287 const RecordVal *V = Reg->getValue("DwarfAlias");
288 if (!V || !V->getValue())
291 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
292 Record *Alias = DI->getDef();
293 DwarfRegNums[Reg] = DwarfRegNums[Alias];
296 // Emit information about the dwarf register numbers.
297 for (unsigned j = 0; j < 2; ++j) {
298 for (unsigned i = 0, e = maxLength; i != e; ++i) {
299 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
300 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
301 OS << i << "L2Dwarf[]";
304 // Store the mapping sorted by the Dwarf reg num so lookup can be done
305 // with a binary search.
306 for (DwarfRegNumsMapTy::iterator
307 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
308 int RegNo = I->second[i];
309 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
312 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
320 // We have to store the size in a const global, it's used in multiple
322 OS << "extern const unsigned " << Namespace
323 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
325 OS << " = sizeof(" << Namespace
326 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
327 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
335 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
336 const std::vector<CodeGenRegister*> &Regs,
338 // Emit the initializer so the tables from EmitRegMappingTables get wired up
339 // to the MCRegisterInfo object.
340 unsigned maxLength = 0;
341 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
342 Record *Reg = Regs[i]->TheDef;
343 maxLength = std::max((size_t)maxLength,
344 Reg->getValueAsListOfInts("DwarfNumbers").size());
350 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
352 // Emit reverse information about the dwarf register numbers.
353 for (unsigned j = 0; j < 2; ++j) {
356 OS << "DwarfFlavour";
361 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
363 for (unsigned i = 0, e = maxLength; i != e; ++i) {
364 OS << " case " << i << ":\n";
369 raw_string_ostream(Tmp) << Namespace
370 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
372 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
383 // Emit information about the dwarf register numbers.
384 for (unsigned j = 0; j < 2; ++j) {
387 OS << "DwarfFlavour";
392 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
394 for (unsigned i = 0, e = maxLength; i != e; ++i) {
395 OS << " case " << i << ":\n";
400 raw_string_ostream(Tmp) << Namespace
401 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
403 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
415 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
416 // Width is the number of bits per hex number.
417 static void printBitVectorAsHex(raw_ostream &OS,
418 const BitVector &Bits,
420 assert(Width <= 32 && "Width too large");
421 unsigned Digits = (Width + 3) / 4;
422 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
424 for (unsigned j = 0; j != Width && i + j != e; ++j)
425 Value |= Bits.test(i + j) << j;
426 OS << format("0x%0*x, ", Digits, Value);
430 // Helper to emit a set of bits into a constant byte array.
431 class BitVectorEmitter {
434 void add(unsigned v) {
435 if (v >= Values.size())
436 Values.resize(((v/8)+1)*8); // Round up to the next byte.
440 void print(raw_ostream &OS) {
441 printBitVectorAsHex(OS, Values, 8);
445 static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
446 OS << getQualifiedName(Reg->TheDef);
449 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
450 OS << getEnumName(VT);
454 // runMCDesc - Print out MC register descriptions.
457 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
458 CodeGenRegBank &RegBank) {
459 EmitSourceFileHeader("MC Register Information", OS);
461 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
462 OS << "#undef GET_REGINFO_MC_DESC\n";
464 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
465 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
466 RegBank.computeOverlaps(Overlaps);
468 // The lists of sub-registers, super-registers, and overlaps all go in the
469 // same array. That allows us to share suffixes.
470 typedef std::vector<const CodeGenRegister*> RegVec;
471 SmallVector<RegVec, 4> SubRegLists(Regs.size());
472 SmallVector<RegVec, 4> OverlapLists(Regs.size());
473 SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
475 // Precompute register lists for the SequenceToOffsetTable.
476 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
477 const CodeGenRegister *Reg = Regs[i];
479 // Compute the ordered sub-register list.
480 SetVector<const CodeGenRegister*> SR;
481 Reg->addSubRegsPreOrder(SR, RegBank);
482 RegVec &SubRegList = SubRegLists[i];
483 SubRegList.assign(SR.begin(), SR.end());
484 RegSeqs.add(SubRegList);
486 // Super-registers are already computed.
487 const RegVec &SuperRegList = Reg->getSuperRegs();
488 RegSeqs.add(SuperRegList);
490 // The list of overlaps doesn't need to have any particular order, except
491 // Reg itself must be the first element. Pick an ordering that has one of
492 // the other lists as a suffix.
493 RegVec &OverlapList = OverlapLists[i];
494 const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
495 SubRegList : SuperRegList;
496 CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
498 // First element is Reg itself.
499 OverlapList.push_back(Reg);
502 // Any elements not in Suffix.
503 const CodeGenRegister::Set &OSet = Overlaps[Reg];
504 std::set_difference(OSet.begin(), OSet.end(),
505 Omit.begin(), Omit.end(),
506 std::back_inserter(OverlapList),
507 CodeGenRegister::Less());
509 // Finally, Suffix itself.
510 OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
511 RegSeqs.add(OverlapList);
514 // Compute the final layout of the sequence table.
517 OS << "namespace llvm {\n\n";
519 const std::string &TargetName = Target.getName();
521 // Emit the shared table of register lists.
522 OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
523 RegSeqs.emit(OS, printRegister);
526 OS << "extern const MCRegisterDesc " << TargetName
527 << "RegDesc[] = { // Descriptors\n";
528 OS << " { \"NOREG\", 0, 0, 0 },\n";
530 // Emit the register descriptors now.
531 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
532 const CodeGenRegister *Reg = Regs[i];
533 OS << " { \"" << Reg->getName() << "\", "
534 << RegSeqs.get(OverlapLists[i]) << ", "
535 << RegSeqs.get(SubRegLists[i]) << ", "
536 << RegSeqs.get(Reg->getSuperRegs()) << " },\n";
538 OS << "};\n\n"; // End of register descriptors...
540 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
542 // Loop over all of the register classes... emitting each one.
543 OS << "namespace { // Register classes...\n";
545 // Emit the register enum value arrays for each RegisterClass
546 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
547 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
548 ArrayRef<Record*> Order = RC.getOrder();
550 // Give the register class a legal C name if it's anonymous.
551 std::string Name = RC.getName();
553 // Emit the register list now.
554 OS << " // " << Name << " Register Class...\n"
555 << " const uint16_t " << Name
557 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
558 Record *Reg = Order[i];
559 OS << getQualifiedName(Reg) << ", ";
563 OS << " // " << Name << " Bit set.\n"
564 << " const uint8_t " << Name
566 BitVectorEmitter BVE;
567 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
568 Record *Reg = Order[i];
569 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
577 OS << "extern const MCRegisterClass " << TargetName
578 << "MCRegisterClasses[] = {\n";
580 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
581 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
583 // Asserts to make sure values will fit in table assuming types from
585 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
586 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
587 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
589 OS << " { " << '\"' << RC.getName() << "\", "
590 << RC.getName() << ", " << RC.getName() << "Bits, "
591 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
592 << RC.getQualifiedName() + "RegClassID" << ", "
593 << RC.SpillSize/8 << ", "
594 << RC.SpillAlignment/8 << ", "
595 << RC.CopyCost << ", "
596 << RC.Allocatable << " },\n";
601 // Emit the data table for getSubReg().
602 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
603 if (SubRegIndices.size()) {
604 OS << "const uint16_t " << TargetName << "SubRegTable[]["
605 << SubRegIndices.size() << "] = {\n";
606 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
607 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
608 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
614 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
615 // FIXME: We really should keep this to 80 columns...
616 CodeGenRegister::SubRegMap::const_iterator SubReg =
617 SRM.find(SubRegIndices[j]);
618 if (SubReg != SRM.end())
619 OS << getQualifiedName(SubReg->second->TheDef);
625 OS << "}" << (i != e ? "," : "") << "\n";
628 OS << "const uint16_t *get" << TargetName
629 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
630 << "SubRegTable;\n}\n\n";
633 EmitRegMappingTables(OS, Regs, false);
635 // MCRegisterInfo initialization routine.
636 OS << "static inline void Init" << TargetName
637 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
638 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
639 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
640 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
641 << RegisterClasses.size() << ", " << TargetName << "RegLists, ";
642 if (SubRegIndices.size() != 0)
643 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
644 << SubRegIndices.size() << ");\n\n";
646 OS << "NULL, 0);\n\n";
648 EmitRegMapping(OS, Regs, false);
652 OS << "} // End llvm namespace \n";
653 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
657 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
658 CodeGenRegBank &RegBank) {
659 EmitSourceFileHeader("Register Information Header Fragment", OS);
661 OS << "\n#ifdef GET_REGINFO_HEADER\n";
662 OS << "#undef GET_REGINFO_HEADER\n";
664 const std::string &TargetName = Target.getName();
665 std::string ClassName = TargetName + "GenRegisterInfo";
667 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
669 OS << "namespace llvm {\n\n";
671 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
672 << " explicit " << ClassName
673 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
674 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
675 << " { return false; }\n"
676 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
677 << " const TargetRegisterClass *"
678 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
679 << " const TargetRegisterClass *getMatchingSuperRegClass("
680 "const TargetRegisterClass*, const TargetRegisterClass*, "
682 << " const RegClassWeight &getRegClassWeight("
683 << "const TargetRegisterClass *RC) const;\n"
684 << " unsigned getNumRegPressureSets() const;\n"
685 << " const char *getRegPressureSetName(unsigned Idx) const;\n"
686 << " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
687 << " const int *getRegClassPressureSets("
688 << "const TargetRegisterClass *RC) const;\n"
691 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
693 if (!RegisterClasses.empty()) {
694 OS << "namespace " << RegisterClasses[0]->Namespace
695 << " { // Register classes\n";
697 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
698 const CodeGenRegisterClass &RC = *RegisterClasses[i];
699 const std::string &Name = RC.getName();
701 // Output the extern for the instance.
702 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
704 OS << "} // end of namespace " << TargetName << "\n\n";
706 OS << "} // End llvm namespace \n";
707 OS << "#endif // GET_REGINFO_HEADER\n\n";
711 // runTargetDesc - Output the target register and register file descriptions.
714 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
715 CodeGenRegBank &RegBank){
716 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
718 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
719 OS << "#undef GET_REGINFO_TARGET_DESC\n";
721 OS << "namespace llvm {\n\n";
723 // Get access to MCRegisterClass data.
724 OS << "extern const MCRegisterClass " << Target.getName()
725 << "MCRegisterClasses[];\n";
727 // Start out by emitting each of the register classes.
728 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
730 // Collect all registers belonging to any allocatable class.
731 std::set<Record*> AllocatableRegs;
733 // Collect allocatable registers.
734 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
735 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
736 ArrayRef<Record*> Order = RC.getOrder();
739 AllocatableRegs.insert(Order.begin(), Order.end());
742 // Build a shared array of value types.
743 SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
744 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
745 VTSeqs.add(RegisterClasses[rc]->VTs);
747 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
748 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
751 // Now that all of the structs have been emitted, emit the instances.
752 if (!RegisterClasses.empty()) {
753 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
755 OS << "\nstatic const TargetRegisterClass *const "
756 << "NullRegClasses[] = { NULL };\n\n";
758 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
760 if (NumSubRegIndices) {
761 // Compute the super-register classes for each RegisterClass
762 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
763 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
764 for (DenseMap<Record*,Record*>::const_iterator
765 i = RC.SubRegClasses.begin(),
766 e = RC.SubRegClasses.end(); i != e; ++i) {
767 // Find the register class number of i->second for SuperRegClassMap.
768 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
769 assert(RC2 && "Invalid register class in SubRegClasses");
770 SuperRegClassMap[RC2->EnumValue].insert(rc);
774 // Emit the super-register classes for each RegisterClass
775 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
776 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
778 // Give the register class a legal C name if it's anonymous.
779 std::string Name = RC.getName();
782 << " Super-register Classes...\n"
783 << "static const TargetRegisterClass *const "
784 << Name << "SuperRegClasses[] = {\n ";
787 std::map<unsigned, std::set<unsigned> >::iterator I =
788 SuperRegClassMap.find(rc);
789 if (I != SuperRegClassMap.end()) {
790 for (std::set<unsigned>::iterator II = I->second.begin(),
791 EE = I->second.end(); II != EE; ++II) {
792 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
795 OS << "&" << RC2.getQualifiedName() << "RegClass";
800 OS << (!Empty ? ", " : "") << "NULL";
805 // Emit the sub-classes array for each RegisterClass
806 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
807 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
809 // Give the register class a legal C name if it's anonymous.
810 std::string Name = RC.getName();
812 OS << "static const uint32_t " << Name << "SubclassMask[] = {\n ";
813 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
817 // Emit NULL terminated super-class lists.
818 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
819 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
820 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
822 // Skip classes without supers. We can reuse NullRegClasses.
826 OS << "static const TargetRegisterClass *const "
827 << RC.getName() << "Superclasses[] = {\n";
828 for (unsigned i = 0; i != Supers.size(); ++i)
829 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
830 OS << " NULL\n};\n\n";
834 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
835 const CodeGenRegisterClass &RC = *RegisterClasses[i];
836 if (!RC.AltOrderSelect.empty()) {
837 OS << "\nstatic inline unsigned " << RC.getName()
838 << "AltOrderSelect(const MachineFunction &MF) {"
839 << RC.AltOrderSelect << "}\n\n"
840 << "static ArrayRef<uint16_t> " << RC.getName()
841 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
842 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
843 ArrayRef<Record*> Elems = RC.getOrder(oi);
844 if (!Elems.empty()) {
845 OS << " static const uint16_t AltOrder" << oi << "[] = {";
846 for (unsigned elem = 0; elem != Elems.size(); ++elem)
847 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
851 OS << " const MCRegisterClass &MCR = " << Target.getName()
852 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
853 << " const ArrayRef<uint16_t> Order[] = {\n"
854 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
855 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
856 if (RC.getOrder(oi).empty())
857 OS << "),\n ArrayRef<uint16_t>(";
859 OS << "),\n makeArrayRef(AltOrder" << oi;
860 OS << ")\n };\n const unsigned Select = " << RC.getName()
861 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
862 << ");\n return Order[Select];\n}\n";
866 // Now emit the actual value-initialized register class instances.
867 OS << "namespace " << RegisterClasses[0]->Namespace
868 << " { // Register class instances\n";
870 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
871 const CodeGenRegisterClass &RC = *RegisterClasses[i];
872 OS << " extern const TargetRegisterClass "
873 << RegisterClasses[i]->getName() << "RegClass = {\n "
874 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
876 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
877 << RC.getName() << "SubclassMask,\n ";
878 if (RC.getSuperClasses().empty())
879 OS << "NullRegClasses,\n ";
881 OS << RC.getName() << "Superclasses,\n ";
882 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
884 if (RC.AltOrderSelect.empty())
887 OS << RC.getName() << "GetRawAllocationOrder\n";
894 OS << "\nnamespace {\n";
895 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
896 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
897 OS << " &" << RegisterClasses[i]->getQualifiedName()
900 OS << "}\n"; // End of anonymous namespace...
902 // Emit extra information about registers.
903 const std::string &TargetName = Target.getName();
904 OS << "\nstatic const TargetRegisterInfoDesc "
905 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
906 OS << " { 0, 0 },\n";
908 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
909 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
910 const CodeGenRegister &Reg = *Regs[i];
912 OS << Reg.CostPerUse << ", "
913 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
915 OS << "};\n"; // End of register descriptors...
918 // Calculate the mapping of subregister+index pairs to physical registers.
919 // This will also create further anonymous indices.
920 unsigned NamedIndices = RegBank.getNumNamedIndices();
922 // Emit SubRegIndex names, skipping 0
923 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
924 OS << "\nstatic const char *const " << TargetName
925 << "SubRegIndexTable[] = { \"";
926 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
927 OS << SubRegIndices[i]->getName();
933 // Emit names of the anonymous subreg indices.
934 if (SubRegIndices.size() > NamedIndices) {
936 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
937 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
945 std::string ClassName = Target.getName() + "GenRegisterInfo";
947 // Emit composeSubRegIndices
948 OS << "unsigned " << ClassName
949 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
950 << " switch (IdxA) {\n"
951 << " default:\n return IdxB;\n";
952 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
954 for (unsigned j = 0; j != e; ++j) {
955 if (CodeGenSubRegIndex *Comp =
956 SubRegIndices[i]->compose(SubRegIndices[j])) {
958 OS << " case " << SubRegIndices[i]->getQualifiedName()
959 << ": switch(IdxB) {\n default: return IdxB;\n";
962 OS << " case " << SubRegIndices[j]->getQualifiedName()
963 << ": return " << Comp->getQualifiedName() << ";\n";
971 // Emit getSubClassWithSubReg.
972 OS << "const TargetRegisterClass *" << ClassName
973 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
975 if (SubRegIndices.empty()) {
976 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
979 // Use the smallest type that can hold a regclass ID with room for a
981 if (RegisterClasses.size() < UINT8_MAX)
982 OS << " static const uint8_t Table[";
983 else if (RegisterClasses.size() < UINT16_MAX)
984 OS << " static const uint16_t Table[";
986 throw "Too many register classes.";
987 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
988 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
989 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
990 OS << " {\t// " << RC.getName() << "\n";
991 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
992 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
993 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
994 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
995 << " -> " << SRC->getName() << "\n";
997 OS << " 0,\t// " << Idx->getName() << "\n";
1001 OS << " };\n assert(RC && \"Missing regclass\");\n"
1002 << " if (!Idx) return RC;\n --Idx;\n"
1003 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1004 << " unsigned TV = Table[RC->getID()][Idx];\n"
1005 << " return TV ? getRegClass(TV - 1) : 0;\n";
1009 // Emit getMatchingSuperRegClass.
1010 OS << "const TargetRegisterClass *" << ClassName
1011 << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
1012 " const TargetRegisterClass *B, unsigned Idx) const {\n";
1013 if (SubRegIndices.empty()) {
1014 OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
1016 // We need to find the largest sub-class of A such that every register has
1017 // an Idx sub-register in B. Map (B, Idx) to a bit-vector of
1018 // super-register classes that map into B. Then compute the largest common
1019 // sub-class with A by taking advantage of the register class ordering,
1020 // like getCommonSubClass().
1022 // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
1023 // the number of 32-bit words required to represent all register classes.
1024 const unsigned BVWords = (RegisterClasses.size()+31)/32;
1025 BitVector BV(RegisterClasses.size());
1027 OS << " static const uint32_t Table[" << RegisterClasses.size()
1028 << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
1029 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1030 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1031 OS << " {\t// " << RC.getName() << "\n";
1032 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1033 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1035 RC.getSuperRegClasses(Idx, BV);
1037 printBitVectorAsHex(OS, BV, 32);
1038 OS << "},\t// " << Idx->getName() << '\n';
1042 OS << " };\n assert(A && B && \"Missing regclass\");\n"
1044 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1045 << " const uint32_t *TV = Table[B->getID()][Idx];\n"
1046 << " const uint32_t *SC = A->getSubClassMask();\n"
1047 << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
1048 << " if (unsigned Common = TV[i] & SC[i])\n"
1049 << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
1054 EmitRegUnitPressure(OS, RegBank, ClassName);
1056 // Emit the constructor of the class...
1057 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1058 OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
1059 if (SubRegIndices.size() != 0)
1060 OS << "extern const uint16_t *get" << TargetName
1061 << "SubRegTable();\n";
1063 EmitRegMappingTables(OS, Regs, true);
1065 OS << ClassName << "::\n" << ClassName
1066 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1067 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1068 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1069 << " " << TargetName << "SubRegIndexTable) {\n"
1070 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1071 << Regs.size()+1 << ", RA,\n " << TargetName
1072 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1073 << " " << TargetName << "RegLists,\n"
1075 if (SubRegIndices.size() != 0)
1076 OS << "get" << TargetName << "SubRegTable(), "
1077 << SubRegIndices.size() << ");\n\n";
1079 OS << "NULL, 0);\n\n";
1081 EmitRegMapping(OS, Regs, true);
1086 // Emit CalleeSavedRegs information.
1087 std::vector<Record*> CSRSets =
1088 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1089 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1090 Record *CSRSet = CSRSets[i];
1091 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1092 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1094 // Emit the *_SaveList list of callee-saved registers.
1095 OS << "static const uint16_t " << CSRSet->getName()
1096 << "_SaveList[] = { ";
1097 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1098 OS << getQualifiedName((*Regs)[r]) << ", ";
1101 // Emit the *_RegMask bit mask of call-preserved registers.
1102 OS << "static const uint32_t " << CSRSet->getName()
1103 << "_RegMask[] = { ";
1104 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1109 OS << "} // End llvm namespace \n";
1110 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1113 void RegisterInfoEmitter::run(raw_ostream &OS) {
1114 CodeGenTarget Target(Records);
1115 CodeGenRegBank &RegBank = Target.getRegBank();
1116 RegBank.computeDerivedInfo();
1118 runEnums(OS, Target, RegBank);
1119 runMCDesc(OS, Target, RegBank);
1120 runTargetHeader(OS, Target, RegBank);
1121 runTargetDesc(OS, Target, RegBank);