1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
28 CodeGenTarget Target(Records);
29 CodeGenRegBank &Bank = Target.getRegBank();
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
37 if (!Namespace.empty())
38 OS << "namespace " << Namespace << " {\n";
39 OS << "enum {\n NoRegister,\n";
41 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
42 OS << " " << Registers[i].getName() << " = " <<
43 Registers[i].EnumValue << ",\n";
44 assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
45 "Register enum value mismatch!");
46 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
48 if (!Namespace.empty())
51 const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices();
52 if (!SubRegIndices.empty()) {
53 OS << "\n// Subregister indices\n";
54 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
55 if (!Namespace.empty())
56 OS << "namespace " << Namespace << " {\n";
57 OS << "enum {\n NoSubRegister,\n";
58 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
59 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
60 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
62 if (!Namespace.empty())
65 OS << "} // End llvm namespace \n";
68 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
69 EmitSourceFileHeader("Register Information Header Fragment", OS);
70 CodeGenTarget Target(Records);
71 const std::string &TargetName = Target.getName();
72 std::string ClassName = TargetName + "GenRegisterInfo";
74 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
75 OS << "#include <string>\n\n";
77 OS << "namespace llvm {\n\n";
79 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
80 << " explicit " << ClassName
81 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
82 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
83 << "unsigned Flavour) const;\n"
84 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
85 << "unsigned Flavour) const;\n"
86 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
87 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
88 << " { return false; }\n"
89 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
90 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
91 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
94 const std::vector<CodeGenRegisterClass> &RegisterClasses =
95 Target.getRegisterClasses();
97 if (!RegisterClasses.empty()) {
98 OS << "namespace " << RegisterClasses[0].Namespace
99 << " { // Register classes\n";
102 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
104 OS << " " << RegisterClasses[i].getName() << "RegClassID";
109 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
110 const std::string &Name = RegisterClasses[i].getName();
112 // Output the register class definition.
113 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
114 << " " << Name << "Class();\n"
115 << RegisterClasses[i].MethodProtos << " };\n";
117 // Output the extern for the instance.
118 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
119 // Output the extern for the pointer to the instance (should remove).
120 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
121 << Name << "RegClass;\n";
123 OS << "} // end of namespace " << TargetName << "\n\n";
125 OS << "} // End llvm namespace \n";
128 static void addSuperReg(Record *R, Record *S,
129 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
130 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
131 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
133 errs() << "Error: recursive sub-register relationship between"
134 << " register " << getQualifiedName(R)
135 << " and its sub-registers?\n";
138 if (!SuperRegs[R].insert(S).second)
140 SubRegs[S].insert(R);
141 Aliases[R].insert(S);
142 Aliases[S].insert(R);
143 if (SuperRegs.count(S))
144 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
145 E = SuperRegs[S].end(); I != E; ++I)
146 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
149 static void addSubSuperReg(Record *R, Record *S,
150 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
151 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
152 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
154 errs() << "Error: recursive sub-register relationship between"
155 << " register " << getQualifiedName(R)
156 << " and its sub-registers?\n";
160 if (!SubRegs[R].insert(S).second)
162 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
163 Aliases[R].insert(S);
164 Aliases[S].insert(R);
165 if (SubRegs.count(S))
166 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
167 E = SubRegs[S].end(); I != E; ++I)
168 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
171 struct RegisterMaps {
172 // Map SubRegIndex -> Register
173 typedef std::map<Record*, Record*, LessRecord> SubRegMap;
174 // Map Register -> SubRegMap
175 typedef std::map<Record*, SubRegMap> SubRegMaps;
178 SubRegMap &inferSubRegIndices(Record *Reg, CodeGenTarget &);
180 // Composite SubRegIndex instances.
181 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
182 typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
183 CompositeMap Composite;
185 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
187 void computeComposites();
190 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
191 RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg,
192 CodeGenTarget &Target) {
193 SubRegMap &SRM = SubReg[Reg];
196 std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
197 std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
198 if (SubRegs.size() != Indices.size())
199 throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
201 // First insert the direct subregs and make sure they are fully indexed.
202 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
203 if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
204 throw "SubRegIndex " + Indices[i]->getName()
205 + " appears twice in Register " + Reg->getName();
206 inferSubRegIndices(SubRegs[i], Target);
209 // Keep track of inherited subregs and how they can be reached.
210 // Register -> (SubRegIndex, SubRegIndex)
211 typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
214 // Clone inherited subregs. Here the order is important - earlier subregs take
216 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
217 SubRegMap &M = SubReg[SubRegs[i]];
218 for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
219 if (!SRM.insert(*si).second)
220 Orphans[si->second] = std::make_pair(Indices[i], si->first);
223 // Finally process the composites.
224 ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
225 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
226 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
228 throw "Invalid dag '" + Comps->getElement(i)->getAsString()
229 + "' in CompositeIndices";
230 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
231 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
232 throw "Invalid SubClassIndex in " + Pat->getAsString();
234 // Resolve list of subreg indices into R2.
236 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
237 de = Pat->arg_end(); di != de; ++di) {
238 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
239 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
240 throw "Invalid SubClassIndex in " + Pat->getAsString();
241 SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
242 if (ni == SubReg[R2].end())
243 throw "Composite " + Pat->getAsString() + " refers to bad index in "
248 // Insert composite index. Allow overriding inherited indices etc.
249 SRM[BaseIdxInit->getDef()] = R2;
251 // R2 is now directly addressable, no longer an orphan.
255 // Now Orphans contains the inherited subregisters without a direct index.
256 // Create inferred indexes for all missing entries.
257 for (OrphanMap::iterator I = Orphans.begin(), E = Orphans.end(); I != E;
259 Record *&Comp = Composite[I->second];
261 Comp = Target.getRegBank().getCompositeSubRegIndex(I->second.first,
263 SRM[Comp] = I->first;
269 void RegisterMaps::computeComposites() {
270 for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
272 Record *Reg1 = sri->first;
273 const SubRegMap &SRM1 = sri->second;
274 for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
276 Record *Idx1 = i1->first;
277 Record *Reg2 = i1->second;
278 // Ignore identity compositions.
281 // If Reg2 has no subregs, Idx1 doesn't compose.
282 if (!SubReg.count(Reg2))
284 const SubRegMap &SRM2 = SubReg[Reg2];
285 // Try composing Idx1 with another SubRegIndex.
286 for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
288 std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
289 Record *Reg3 = i2->second;
290 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
291 for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
293 // Ignore identity compositions.
296 if (i1d->second == Reg3) {
297 std::pair<CompositeMap::iterator,bool> Ins =
298 Composite.insert(std::make_pair(IdxPair, i1d->first));
299 // Conflicting composition? Emit a warning but allow it.
300 if (!Ins.second && Ins.first->second != i1d->first) {
301 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
302 << " and " << getQualifiedName(IdxPair.second)
303 << " compose ambiguously as "
304 << getQualifiedName(Ins.first->second) << " or "
305 << getQualifiedName(i1d->first) << "\n";
313 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
314 // compositions, so remove any mappings of that form.
315 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
317 CompositeMap::iterator j = i;
319 if (j->first.second == j->second)
324 class RegisterSorter {
326 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
329 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
330 : RegisterSubRegs(RS) {}
332 bool operator()(Record *RegA, Record *RegB) {
333 // B is sub-register of A.
334 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
338 // RegisterInfoEmitter::run - Main register file description emitter.
340 void RegisterInfoEmitter::run(raw_ostream &OS) {
341 CodeGenTarget Target(Records);
342 CodeGenRegBank &RegBank = Target.getRegBank();
343 EmitSourceFileHeader("Register Information Source Fragment", OS);
345 OS << "namespace llvm {\n\n";
347 // Start out by emitting each of the register classes.
348 const std::vector<CodeGenRegisterClass> &RegisterClasses =
349 Target.getRegisterClasses();
351 // Collect all registers belonging to any allocatable class.
352 std::set<Record*> AllocatableRegs;
354 // Loop over all of the register classes... emitting each one.
355 OS << "namespace { // Register classes...\n";
357 // Emit the register enum value arrays for each RegisterClass
358 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
359 const CodeGenRegisterClass &RC = RegisterClasses[rc];
361 // Collect allocatable registers.
363 AllocatableRegs.insert(RC.Elements.begin(), RC.Elements.end());
365 // Give the register class a legal C name if it's anonymous.
366 std::string Name = RC.TheDef->getName();
368 // Emit the register list now.
369 OS << " // " << Name << " Register Class...\n"
370 << " static const unsigned " << Name
372 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
373 Record *Reg = RC.Elements[i];
374 OS << getQualifiedName(Reg) << ", ";
379 // Emit the ValueType arrays for each RegisterClass
380 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
381 const CodeGenRegisterClass &RC = RegisterClasses[rc];
383 // Give the register class a legal C name if it's anonymous.
384 std::string Name = RC.TheDef->getName() + "VTs";
386 // Emit the register list now.
388 << " Register Class Value Types...\n"
389 << " static const EVT " << Name
391 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
392 OS << getEnumName(RC.VTs[i]) << ", ";
393 OS << "MVT::Other\n };\n\n";
395 OS << "} // end anonymous namespace\n\n";
397 // Now that all of the structs have been emitted, emit the instances.
398 if (!RegisterClasses.empty()) {
399 OS << "namespace " << RegisterClasses[0].Namespace
400 << " { // Register class instances\n";
401 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
402 OS << " " << RegisterClasses[i].getName() << "Class\t"
403 << RegisterClasses[i].getName() << "RegClass;\n";
405 std::map<unsigned, std::set<unsigned> > SuperClassMap;
406 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
409 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
411 if (NumSubRegIndices) {
412 // Emit the sub-register classes for each RegisterClass
413 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
414 const CodeGenRegisterClass &RC = RegisterClasses[rc];
415 std::vector<Record*> SRC(NumSubRegIndices);
416 for (DenseMap<Record*,Record*>::const_iterator
417 i = RC.SubRegClasses.begin(),
418 e = RC.SubRegClasses.end(); i != e; ++i) {
420 unsigned idx = RegBank.getSubRegIndexNo(i->first);
421 SRC.at(idx-1) = i->second;
423 // Find the register class number of i->second for SuperRegClassMap.
424 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
425 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
426 if (RC2.TheDef == i->second) {
427 SuperRegClassMap[rc2].insert(rc);
433 // Give the register class a legal C name if it's anonymous.
434 std::string Name = RC.TheDef->getName();
437 << " Sub-register Classes...\n"
438 << " static const TargetRegisterClass* const "
439 << Name << "SubRegClasses[] = {\n ";
441 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
445 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
452 // Emit the super-register classes for each RegisterClass
453 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
454 const CodeGenRegisterClass &RC = RegisterClasses[rc];
456 // Give the register class a legal C name if it's anonymous.
457 std::string Name = RC.TheDef->getName();
460 << " Super-register Classes...\n"
461 << " static const TargetRegisterClass* const "
462 << Name << "SuperRegClasses[] = {\n ";
465 std::map<unsigned, std::set<unsigned> >::iterator I =
466 SuperRegClassMap.find(rc);
467 if (I != SuperRegClassMap.end()) {
468 for (std::set<unsigned>::iterator II = I->second.begin(),
469 EE = I->second.end(); II != EE; ++II) {
470 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
473 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
478 OS << (!Empty ? ", " : "") << "NULL";
482 // No subregindices in this target
483 OS << " static const TargetRegisterClass* const "
484 << "NullRegClasses[] = { NULL };\n\n";
487 // Emit the sub-classes array for each RegisterClass
488 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
489 const CodeGenRegisterClass &RC = RegisterClasses[rc];
491 // Give the register class a legal C name if it's anonymous.
492 std::string Name = RC.TheDef->getName();
495 << " Register Class sub-classes...\n"
496 << " static const TargetRegisterClass* const "
497 << Name << "Subclasses[] = {\n ";
500 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
501 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
503 // Sub-classes are used to determine if a virtual register can be used
504 // as an instruction operand, or if it must be copied first.
505 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
507 if (!Empty) OS << ", ";
508 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
511 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
512 SuperClassMap.find(rc2);
513 if (SCMI == SuperClassMap.end()) {
514 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
515 SCMI = SuperClassMap.find(rc2);
517 SCMI->second.insert(rc);
520 OS << (!Empty ? ", " : "") << "NULL";
524 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
525 const CodeGenRegisterClass &RC = RegisterClasses[rc];
527 // Give the register class a legal C name if it's anonymous.
528 std::string Name = RC.TheDef->getName();
531 << " Register Class super-classes...\n"
532 << " static const TargetRegisterClass* const "
533 << Name << "Superclasses[] = {\n ";
536 std::map<unsigned, std::set<unsigned> >::iterator I =
537 SuperClassMap.find(rc);
538 if (I != SuperClassMap.end()) {
539 for (std::set<unsigned>::iterator II = I->second.begin(),
540 EE = I->second.end(); II != EE; ++II) {
541 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
542 if (!Empty) OS << ", ";
543 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
548 OS << (!Empty ? ", " : "") << "NULL";
553 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
554 const CodeGenRegisterClass &RC = RegisterClasses[i];
555 OS << RC.MethodBodies << "\n";
556 OS << RC.getName() << "Class::" << RC.getName()
557 << "Class() : TargetRegisterClass("
558 << RC.getName() + "RegClassID" << ", "
559 << '\"' << RC.getName() << "\", "
560 << RC.getName() + "VTs" << ", "
561 << RC.getName() + "Subclasses" << ", "
562 << RC.getName() + "Superclasses" << ", "
563 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
565 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
567 << RC.SpillSize/8 << ", "
568 << RC.SpillAlignment/8 << ", "
569 << RC.CopyCost << ", "
570 << RC.Allocatable << ", "
571 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
578 OS << "\nnamespace {\n";
579 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
580 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
581 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
585 // Emit register sub-registers / super-registers, aliases...
586 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
587 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
588 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
589 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
590 DwarfRegNumsMapTy DwarfRegNums;
592 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
594 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
595 Record *R = Regs[i].TheDef;
596 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
597 // Add information that R aliases all of the elements in the list... and
598 // that everything in the list aliases R.
599 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
601 if (RegisterAliases[R].count(Reg))
602 errs() << "Warning: register alias between " << getQualifiedName(R)
603 << " and " << getQualifiedName(Reg)
604 << " specified multiple times!\n";
605 RegisterAliases[R].insert(Reg);
607 if (RegisterAliases[Reg].count(R))
608 errs() << "Warning: register alias between " << getQualifiedName(R)
609 << " and " << getQualifiedName(Reg)
610 << " specified multiple times!\n";
611 RegisterAliases[Reg].insert(R);
615 // Process sub-register sets.
616 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
617 Record *R = Regs[i].TheDef;
618 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
619 // Process sub-register set and add aliases information.
620 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
621 Record *SubReg = LI[j];
622 if (RegisterSubRegs[R].count(SubReg))
623 errs() << "Warning: register " << getQualifiedName(SubReg)
624 << " specified as a sub-register of " << getQualifiedName(R)
625 << " multiple times!\n";
626 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
631 // Print the SubregHashTable, a simple quadratically probed
632 // hash table for determining if a register is a subregister
633 // of another register.
634 unsigned NumSubRegs = 0;
635 std::map<Record*, unsigned> RegNo;
636 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
637 RegNo[Regs[i].TheDef] = i;
638 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
641 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
642 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
643 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
645 unsigned hashMisses = 0;
647 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
648 Record* R = Regs[i].TheDef;
649 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
650 E = RegisterSubRegs[R].end(); I != E; ++I) {
652 // We have to increase the indices of both registers by one when
653 // computing the hash because, in the generated code, there
654 // will be an extra empty slot at register 0.
655 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
656 unsigned ProbeAmt = 2;
657 while (SubregHashTable[index*2] != ~0U &&
658 SubregHashTable[index*2+1] != ~0U) {
659 index = (index + ProbeAmt) & (SubregHashTableSize-1);
665 SubregHashTable[index*2] = i;
666 SubregHashTable[index*2+1] = RegNo[RJ];
670 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
672 if (SubregHashTableSize) {
673 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
675 OS << " const unsigned SubregHashTable[] = { ";
676 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
678 // Insert spaces for nice formatting.
681 if (SubregHashTable[2*i] != ~0U) {
682 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
683 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
685 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
689 unsigned Idx = SubregHashTableSize*2-2;
690 if (SubregHashTable[Idx] != ~0U) {
692 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
693 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
695 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
698 OS << " const unsigned SubregHashTableSize = "
699 << SubregHashTableSize << ";\n";
701 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
702 << " const unsigned SubregHashTableSize = 1;\n";
705 delete [] SubregHashTable;
708 // Print the AliasHashTable, a simple quadratically probed
709 // hash table for determining if a register aliases another register.
710 unsigned NumAliases = 0;
712 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
713 RegNo[Regs[i].TheDef] = i;
714 NumAliases += RegisterAliases[Regs[i].TheDef].size();
717 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
718 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
719 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
723 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
724 Record* R = Regs[i].TheDef;
725 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
726 E = RegisterAliases[R].end(); I != E; ++I) {
728 // We have to increase the indices of both registers by one when
729 // computing the hash because, in the generated code, there
730 // will be an extra empty slot at register 0.
731 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
732 unsigned ProbeAmt = 2;
733 while (AliasesHashTable[index*2] != ~0U &&
734 AliasesHashTable[index*2+1] != ~0U) {
735 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
741 AliasesHashTable[index*2] = i;
742 AliasesHashTable[index*2+1] = RegNo[RJ];
746 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
748 if (AliasesHashTableSize) {
749 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
751 OS << " const unsigned AliasesHashTable[] = { ";
752 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
754 // Insert spaces for nice formatting.
757 if (AliasesHashTable[2*i] != ~0U) {
758 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
759 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
761 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
765 unsigned Idx = AliasesHashTableSize*2-2;
766 if (AliasesHashTable[Idx] != ~0U) {
768 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
769 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
771 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
774 OS << " const unsigned AliasesHashTableSize = "
775 << AliasesHashTableSize << ";\n";
777 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
778 << " const unsigned AliasesHashTableSize = 1;\n";
781 delete [] AliasesHashTable;
783 if (!RegisterAliases.empty())
784 OS << "\n\n // Register Overlap Lists...\n";
786 // Emit an overlap list for all registers.
787 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
788 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
789 OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { "
790 << getQualifiedName(I->first) << ", ";
791 for (std::set<Record*>::iterator ASI = I->second.begin(),
792 E = I->second.end(); ASI != E; ++ASI)
793 OS << getQualifiedName(*ASI) << ", ";
797 if (!RegisterSubRegs.empty())
798 OS << "\n\n // Register Sub-registers Sets...\n";
800 // Emit the empty sub-registers list
801 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
802 // Loop over all of the registers which have sub-registers, emitting the
803 // sub-registers list to memory.
804 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
805 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
806 if (I->second.empty())
808 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
809 std::vector<Record*> SubRegsVector;
810 for (std::set<Record*>::iterator ASI = I->second.begin(),
811 E = I->second.end(); ASI != E; ++ASI)
812 SubRegsVector.push_back(*ASI);
813 RegisterSorter RS(RegisterSubRegs);
814 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
815 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
816 OS << getQualifiedName(SubRegsVector[i]) << ", ";
820 if (!RegisterSuperRegs.empty())
821 OS << "\n\n // Register Super-registers Sets...\n";
823 // Emit the empty super-registers list
824 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
825 // Loop over all of the registers which have super-registers, emitting the
826 // super-registers list to memory.
827 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
828 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
829 if (I->second.empty())
831 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
833 std::vector<Record*> SuperRegsVector;
834 for (std::set<Record*>::iterator ASI = I->second.begin(),
835 E = I->second.end(); ASI != E; ++ASI)
836 SuperRegsVector.push_back(*ASI);
837 RegisterSorter RS(RegisterSubRegs);
838 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
839 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
840 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
844 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
845 OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
847 // Now that register alias and sub-registers sets have been emitted, emit the
848 // register descriptors now.
849 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
850 const CodeGenRegister &Reg = Regs[i];
852 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
853 if (!RegisterSubRegs[Reg.TheDef].empty())
854 OS << Reg.getName() << "_SubRegsSet,\t";
856 OS << "Empty_SubRegsSet,\t";
857 if (!RegisterSuperRegs[Reg.TheDef].empty())
858 OS << Reg.getName() << "_SuperRegsSet,\t";
860 OS << "Empty_SuperRegsSet,\t";
861 OS << Reg.CostPerUse << ",\t"
862 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
864 OS << " };\n"; // End of register descriptors...
866 // Calculate the mapping of subregister+index pairs to physical registers.
867 // This will also create further anonymous indexes.
868 unsigned NamedIndices = RegBank.getNumNamedIndices();
869 RegisterMaps RegMaps;
870 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
871 RegMaps.inferSubRegIndices(Regs[i].TheDef, Target);
873 // Emit SubRegIndex names, skipping 0
874 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
875 OS << "\n const char *const SubRegIndexTable[] = { \"";
876 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
877 OS << SubRegIndices[i]->getName();
883 // Emit names of the anonymus subreg indexes.
884 if (SubRegIndices.size() > NamedIndices) {
886 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
887 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
893 OS << "}\n\n"; // End of anonymous namespace...
895 std::string ClassName = Target.getName() + "GenRegisterInfo";
897 // Emit the subregister + index mapping function based on the information
899 OS << "unsigned " << ClassName
900 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
901 << " switch (RegNo) {\n"
902 << " default:\n return 0;\n";
903 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
904 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
907 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
908 OS << " switch (Index) {\n";
909 OS << " default: return 0;\n";
910 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
911 ie = SRM.end(); ii != ie; ++ii)
912 OS << " case " << getQualifiedName(ii->first)
913 << ": return " << getQualifiedName(ii->second) << ";\n";
914 OS << " };\n" << " break;\n";
917 OS << " return 0;\n";
920 OS << "unsigned " << ClassName
921 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
922 << " switch (RegNo) {\n"
923 << " default:\n return 0;\n";
924 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
925 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
928 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
929 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
930 ie = SRM.end(); ii != ie; ++ii)
931 OS << " if (SubRegNo == " << getQualifiedName(ii->second)
932 << ") return " << getQualifiedName(ii->first) << ";\n";
933 OS << " return 0;\n";
936 OS << " return 0;\n";
939 // Emit composeSubRegIndices
940 RegMaps.computeComposites();
941 OS << "unsigned " << ClassName
942 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
943 << " switch (IdxA) {\n"
944 << " default:\n return IdxB;\n";
945 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
947 for (unsigned j = 0; j != e; ++j) {
948 if (Record *Comp = RegMaps.Composite.lookup(
949 std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
951 OS << " case " << getQualifiedName(SubRegIndices[i])
952 << ": switch(IdxB) {\n default: return IdxB;\n";
955 OS << " case " << getQualifiedName(SubRegIndices[j])
956 << ": return " << getQualifiedName(Comp) << ";\n";
964 // Emit the constructor of the class...
965 OS << ClassName << "::" << ClassName
966 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
967 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
968 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
969 << " SubRegIndexTable,\n"
970 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
971 << " SubregHashTable, SubregHashTableSize,\n"
972 << " AliasesHashTable, AliasesHashTableSize) {\n"
975 // Collect all information about dwarf register numbers
977 // First, just pull all provided information to the map
978 unsigned maxLength = 0;
979 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
980 Record *Reg = Regs[i].TheDef;
981 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
982 maxLength = std::max((size_t)maxLength, RegNums.size());
983 if (DwarfRegNums.count(Reg))
984 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
985 << "specified multiple times\n";
986 DwarfRegNums[Reg] = RegNums;
989 // Now we know maximal length of number list. Append -1's, where needed
990 for (DwarfRegNumsMapTy::iterator
991 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
992 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
993 I->second.push_back(-1);
995 // Emit reverse information about the dwarf register numbers.
996 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
997 << "unsigned Flavour) const {\n"
998 << " switch (Flavour) {\n"
1000 << " assert(0 && \"Unknown DWARF flavour\");\n"
1003 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1004 OS << " case " << i << ":\n"
1005 << " switch (DwarfRegNum) {\n"
1007 << " assert(0 && \"Invalid DwarfRegNum\");\n"
1010 for (DwarfRegNumsMapTy::iterator
1011 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1012 int DwarfRegNo = I->second[i];
1013 if (DwarfRegNo >= 0)
1014 OS << " case " << DwarfRegNo << ":\n"
1015 << " return " << getQualifiedName(I->first) << ";\n";
1022 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1023 Record *Reg = Regs[i].TheDef;
1024 const RecordVal *V = Reg->getValue("DwarfAlias");
1025 if (!V || !V->getValue())
1028 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
1029 Record *Alias = DI->getDef();
1030 DwarfRegNums[Reg] = DwarfRegNums[Alias];
1033 // Emit information about the dwarf register numbers.
1034 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
1035 << "unsigned Flavour) const {\n"
1036 << " switch (Flavour) {\n"
1038 << " assert(0 && \"Unknown DWARF flavour\");\n"
1041 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1042 OS << " case " << i << ":\n"
1043 << " switch (RegNum) {\n"
1045 << " assert(0 && \"Invalid RegNum\");\n"
1048 // Sort by name to get a stable order.
1051 for (DwarfRegNumsMapTy::iterator
1052 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1053 int RegNo = I->second[i];
1054 OS << " case " << getQualifiedName(I->first) << ":\n"
1055 << " return " << RegNo << ";\n";
1062 OS << "} // End llvm namespace \n";