1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
21 // runEnums - Print out enum values for all of the instructions.
22 void InstrInfoEmitter::runEnums(std::ostream &OS) {
23 EmitSourceFileHeader("Target Instruction Enum Values", OS);
24 OS << "namespace llvm {\n\n";
28 // We must emit the PHI opcode first...
29 std::string Namespace;
30 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
31 E = Target.inst_end(); II != E; ++II) {
32 if (II->second.Namespace != "TargetInstrInfo") {
33 Namespace = II->second.Namespace;
38 if (Namespace.empty()) {
39 std::cerr << "No instructions defined!\n";
43 std::vector<const CodeGenInstruction*> NumberedInstructions;
44 Target.getInstructionsByEnumValue(NumberedInstructions);
46 OS << "namespace " << Namespace << " {\n";
48 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
49 OS << " " << NumberedInstructions[i]->TheDef->getName()
50 << "\t= " << i << ",\n";
52 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
54 OS << "} // End llvm namespace \n";
57 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
58 unsigned Num, std::ostream &OS) const {
59 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
60 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
61 OS << getQualifiedName(Uses[i]) << ", ";
65 static std::vector<std::pair<Record*, unsigned> >
66 GetOperandInfo(const CodeGenInstruction &Inst) {
67 std::vector<std::pair<Record*, unsigned> > Result;
68 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
69 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
70 Result.push_back(std::make_pair(Inst.OperandList[i].Rec,
71 Inst.ConstraintsList[i]));
73 // This might be a multiple operand thing.
74 // Targets like X86 have registers in their multi-operand operands.
75 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
76 unsigned NumDefs = MIOI->getNumArgs();
77 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
79 Result.push_back(std::make_pair((Record*)0, Inst.ConstraintsList[i]));
81 DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
82 Result.push_back(std::make_pair(Def ? Def->getDef() : 0,
83 Inst.ConstraintsList[i]));
89 // For backward compatibility: isTwoAddress means operand 1 is tied to
91 if (Inst.isTwoAddress)
92 Result[1].second |= 1;
98 // run - Emit the main instruction description records for the target...
99 void InstrInfoEmitter::run(std::ostream &OS) {
102 EmitSourceFileHeader("Target Instruction Descriptors", OS);
103 OS << "namespace llvm {\n\n";
105 CodeGenTarget Target;
106 const std::string &TargetName = Target.getName();
107 Record *InstrInfo = Target.getInstructionSet();
109 // Keep track of all of the def lists we have emitted already.
110 std::map<std::vector<Record*>, unsigned> EmittedLists;
111 unsigned ListNumber = 0;
113 // Emit all of the instruction's implicit uses and defs.
114 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
115 E = Target.inst_end(); II != E; ++II) {
116 Record *Inst = II->second.TheDef;
117 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
119 unsigned &IL = EmittedLists[Uses];
120 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
122 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
124 unsigned &IL = EmittedLists[Defs];
125 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
129 std::map<std::vector<std::pair<Record*, unsigned> >, unsigned>
131 unsigned OperandListNum = 0;
132 OperandInfosEmitted[std::vector<std::pair<Record*, unsigned> >()] =
135 // Emit all of the operand info records.
137 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
138 E = Target.inst_end(); II != E; ++II) {
139 std::vector<std::pair<Record*, unsigned> > OperandInfo =
140 GetOperandInfo(II->second);
141 unsigned &N = OperandInfosEmitted[OperandInfo];
143 N = ++OperandListNum;
144 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
145 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
146 Record *RC = OperandInfo[i].first;
147 // FIXME: We only care about register operands for now.
148 if (RC && RC->isSubClassOf("RegisterClass"))
149 OS << "{ " << getQualifiedName(RC) << "RegClassID, 0, ";
150 else if (RC && RC->getName() == "ptr_rc")
151 // Ptr value whose register class is resolved via callback.
155 OS << OperandInfo[i].second << " }, ";
161 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
163 OS << "\nstatic const TargetInstrDescriptor " << TargetName
165 std::vector<const CodeGenInstruction*> NumberedInstructions;
166 Target.getInstructionsByEnumValue(NumberedInstructions);
168 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
169 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
170 OperandInfosEmitted, OS);
172 OS << "} // End llvm namespace \n";
175 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
177 std::map<std::vector<Record*>, unsigned> &EmittedLists,
178 std::map<std::vector<std::pair<Record*,unsigned> >, unsigned> &OpInfo,
181 if (!Inst.OperandList.empty())
182 // Each logical operand can be multiple MI operands.
183 MinOperands = Inst.OperandList.back().MIOperandNo +
184 Inst.OperandList.back().MINumOperands;
189 if (Inst.Name.empty())
190 OS << Inst.TheDef->getName();
194 unsigned ItinClass = !IsItineraries ? 0 :
195 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
197 OS << "\",\t" << MinOperands << ", " << ItinClass
200 // Try to determine (from the pattern), if the instruction is a store.
201 bool isStore = false;
202 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
203 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
204 if (LI && LI->getSize() > 0) {
205 DagInit *Dag = (DagInit *)LI->getElement(0);
206 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
208 Record *Operator = OpDef->getDef();
209 if (Operator->isSubClassOf("SDNode")) {
210 const std::string Opcode = Operator->getValueAsString("Opcode");
211 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
218 // Emit all of the target indepedent flags...
219 if (Inst.isReturn) OS << "|M_RET_FLAG";
220 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
221 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
222 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
223 if (Inst.isCall) OS << "|M_CALL_FLAG";
224 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
225 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
226 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
227 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
228 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
229 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
230 if (Inst.usesCustomDAGSchedInserter)
231 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
232 if (Inst.hasVariableNumberOfOperands)
233 OS << "|M_VARIABLE_OPS";
236 // Emit all of the target-specific flags...
237 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
238 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
239 if (LI->getSize() != Shift->getSize())
240 throw "Lengths of " + InstrInfo->getName() +
241 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
243 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
244 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
245 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
249 // Emit the implicit uses and defs lists...
250 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
254 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
256 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
260 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
262 // Emit the operand info.
263 std::vector<std::pair<Record*,unsigned> > OperandInfo = GetOperandInfo(Inst);
264 if (OperandInfo.empty())
267 OS << "OperandInfo" << OpInfo[OperandInfo];
269 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
273 bool operator()(const Record *Rec1, const Record *Rec2) const {
274 return Rec1->getName() < Rec2->getName();
277 void InstrInfoEmitter::GatherItinClasses() {
278 std::vector<Record*> DefList =
279 Records.getAllDerivedDefinitions("InstrItinClass");
280 IsItineraries = !DefList.empty();
282 if (!IsItineraries) return;
284 std::sort(DefList.begin(), DefList.end(), LessRecord());
286 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
287 Record *Def = DefList[i];
288 ItinClassMap[Def->getName()] = i;
292 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
293 return ItinClassMap[ItinName];
296 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
297 IntInit *ShiftInt, std::ostream &OS) {
298 if (Val == 0 || ShiftInt == 0)
299 throw std::string("Illegal value or shift amount in TargetInfo*!");
300 RecordVal *RV = R->getValue(Val->getValue());
301 int Shift = ShiftInt->getValue();
303 if (RV == 0 || RV->getValue() == 0) {
304 // This isn't an error if this is a builtin instruction.
305 if (R->getName() != "PHI" && R->getName() != "INLINEASM")
306 throw R->getName() + " doesn't have a field named '" +
307 Val->getValue() + "'!";
311 Init *Value = RV->getValue();
312 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
313 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
315 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
316 // Convert the Bits to an integer to print...
317 Init *I = BI->convertInitializerTo(new IntRecTy());
319 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
320 if (II->getValue()) {
322 OS << "|(" << II->getValue() << "<<" << Shift << ")";
324 OS << "|" << II->getValue();
329 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
330 if (II->getValue()) {
332 OS << "|(" << II->getValue() << "<<" << Shift << ")";
334 OS << II->getValue();
339 std::cerr << "Unhandled initializer: " << *Val << "\n";
340 throw "In record '" + R->getName() + "' for TSFlag emission.";